文件名称:ddr3_mig8

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2018-01-18
  • 文件大小:
  • 15.37mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 大**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

fpga实现ddr数据收发测试,完整的工程,下载解压后,即可正确运行,已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)
相关搜索: DDR
verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
ddr3_mig8\1.ipf 21127 2016-01-12
ddr3_mig8\ddr3_mig.gise 14318 2016-01-21
ddr3_mig8\ddr3_mig.xise 51206 2016-01-09
ddr3_mig8\example_top.bgn 37668 2016-01-21
ddr3_mig8\example_top.bit 13058352 2016-01-21
ddr3_mig8\example_top.bld 7073 2016-01-21
ddr3_mig8\example_top.cmd_log 32658 2016-01-21
ddr3_mig8\example_top.cpj 303108 2016-01-21
ddr3_mig8\example_top.drc 29399 2016-01-21
ddr3_mig8\example_top.lso 6 2016-01-21
ddr3_mig8\example_top.ncd 4539749 2016-01-21
ddr3_mig8\example_top.ngc 4498974 2016-01-21
ddr3_mig8\example_top.ngd 11003419 2016-01-21
ddr3_mig8\example_top.ngr 6008732 2016-01-21
ddr3_mig8\example_top.pad 64577 2016-01-21
ddr3_mig8\example_top.par 42240 2016-01-21
ddr3_mig8\example_top.pcf 1127521 2016-01-21
ddr3_mig8\example_top.prj 4144 2016-01-21
ddr3_mig8\example_top.ptwx 20956 2016-01-21
ddr3_mig8\example_top.stx 0 2016-01-21
ddr3_mig8\example_top.syr 630913 2016-01-21
ddr3_mig8\example_top.twr 75491 2016-01-21
ddr3_mig8\example_top.twx 92426 2016-01-21
ddr3_mig8\example_top.unroutes 9753 2016-01-21
ddr3_mig8\example_top.ut 743 2016-01-21
ddr3_mig8\example_top.xpi 45 2016-01-21
ddr3_mig8\example_top.xst 1107 2016-01-21
ddr3_mig8\example_top_bitgen.xwbt 253 2016-01-21
ddr3_mig8\example_top_envsettings.html 17777 2016-01-21
ddr3_mig8\example_top_guide.ncd 4539749 2016-01-21
ddr3_mig8\example_top_map.map 57525 2016-01-21
ddr3_mig8\example_top_map.mrp 606652 2016-01-21
ddr3_mig8\example_top_map.ncd 2215256 2016-01-21
ddr3_mig8\example_top_map.ngm 20896888 2016-01-21
ddr3_mig8\example_top_map.xrpt 85269 2016-01-21
ddr3_mig8\example_top_ngdbuild.xrpt 27711 2016-01-21
ddr3_mig8\example_top_pad.csv 64610 2016-01-21
ddr3_mig8\example_top_pad.txt 373329 2016-01-21
ddr3_mig8\example_top_par.xrpt 714123 2016-01-21
ddr3_mig8\example_top_summary.html 21435 2016-01-21
ddr3_mig8\example_top_summary.xml 409 2016-01-21
ddr3_mig8\example_top_usage.xml 181597 2016-01-21
ddr3_mig8\example_top_xst.xrpt 23229 2016-01-21
ddr3_mig8\impact.xsl 1477 2016-01-12
ddr3_mig8\impact_impact.xwbt 238 2016-01-12
ddr3_mig8\ipcore_dir\coregen.cgc 87281 2016-01-21
ddr3_mig8\ipcore_dir\coregen.cgp 239 2016-01-21
ddr3_mig8\ipcore_dir\coregen.log 2867 2016-01-21
ddr3_mig8\ipcore_dir\create_ddr3_mig_top.tcl 1279 2016-01-05
ddr3_mig8\ipcore_dir\create_ddr3_top.tcl 1275 2016-01-05
ddr3_mig8\ipcore_dir\create_fifo_ddr3.tcl 1272 2016-01-09
ddr3_mig8\ipcore_dir\create_icon.tcl 1333 2016-01-09
ddr3_mig8\ipcore_dir\create_ila.tcl 1336 2016-01-09
ddr3_mig8\ipcore_dir\create_sys_clk_pll.tcl 1262 2016-01-05
ddr3_mig8\ipcore_dir\create_vio_async.tcl 1332 2016-01-09
ddr3_mig8\ipcore_dir\ddr3_eg.ucf 4685 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\docs\ds186.pdf 80353 2012-12-18
ddr3_mig8\ipcore_dir\ddr3_top\docs\ug406.pdf 80480 2012-12-18
ddr3_mig8\ipcore_dir\ddr3_top\example_design\datasheet.txt 3474 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\log.txt 10788 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\mig.prj 15396 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\bitgen_options.ut 692 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\constraints.xcf 287 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\create_ise.bat 3301 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\example_top.cdc 61186 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\example_top.ucf 21469 2016-01-20
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\icon5_cg.xco 1382 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\ila384_8_cg.xco 3863 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\ise_flow.bat 4304 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\makeproj.bat 28 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\readme.txt 4707 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\rem_files.bat 8958 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\set_ise_prop.tcl 11012 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\vio_async_in256_cg.xco 1580 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\vio_sync_out32_cg.xco 1578 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\par\xst_options.txt 1134 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\arb_mux.v 17638 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\arb_row_col.v 12632 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\arb_select.v 19071 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\bank_cntrl.v 25514 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\bank_common.v 17378 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\bank_compare.v 10777 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\bank_mach.v 31023 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\bank_queue.v 22551 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\bank_state.v 36555 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\col_mach.v 18166 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\mc.v 39300 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\rank_cntrl.v 16480 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\rank_common.v 15105 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\rank_mach.v 11024 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\controller\round_robin_arb.v 7531 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ecc\ecc_buf.v 6156 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ecc\ecc_dec_fix.v 6411 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ecc\ecc_gen.v 7893 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ecc\ecc_merge_enc.v 5628 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ip_top\clk_ibuf.v 4264 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ip_top\ddr2_ddr3_chipscope.v 4014 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ip_top\example_top.v 39955 2016-01-21
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ip_top\infrastructure.v 13844 2016-01-05
ddr3_mig8\ipcore_dir\ddr3_top\example_design\rtl\ip_top\iodelay_ctrl.v 7645 2016-01-06

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