文件名称:simulation2
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2017-10-12
- 文件大小：
- 32kb
- 下载次数：
- 0次
- 提 供 者：
- happyw*******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
7segment ctrl testbench and velilog
相关搜索： 7seg
(系统自动生成,下载前可以参看下载内容)
下载文件列表
seg_bcd.v
seg_bcd.v.bak
seg_crt.cr.mti
seg_crt.mpf
seg_crt.v.bak
seg_ctrl.v
seg_ctrl.v.bak
work
work\@b@c@d_to_7segment
work\@b@c@d_to_7segment\_primary.dat
work\@b@c@d_to_7segment\_primary.dbs
work\@b@c@d_to_7segment\_primary.vhd
work\@b@c@d_to_7segment\verilog.prw
work\@b@c@d_to_7segment\verilog.psm
work\@l@a@b05
work\@l@a@b05\_primary.dat
work\@l@a@b05\_primary.dbs
work\@l@a@b05\_primary.vhd
work\@l@a@b05\verilog.prw
work\@l@a@b05\verilog.psm
work\@seven@seg_@c@t@r@l
work\@seven@seg_@c@t@r@l\_primary.dat
work\@seven@seg_@c@t@r@l\_primary.dbs
work\@seven@seg_@c@t@r@l\_primary.vhd
work\@seven@seg_@c@t@r@l\verilog.prw
work\@seven@seg_@c@t@r@l\verilog.psm
work\_info
work\_temp
work\_vmake
work\binary_to_@b@c@d
work\binary_to_@b@c@d\_primary.dat
work\binary_to_@b@c@d\_primary.dbs
work\binary_to_@b@c@d\_primary.vhd
work\binary_to_@b@c@d\verilog.prw
work\binary_to_@b@c@d\verilog.psm
work\linedecoder
work\linedecoder\_primary.dat
work\linedecoder\_primary.dbs
work\linedecoder\_primary.vhd
work\linedecoder\verilog.prw
work\linedecoder\verilog.psm
seg_bcd.v.bak
seg_crt.cr.mti
seg_crt.mpf
seg_crt.v.bak
seg_ctrl.v
seg_ctrl.v.bak
work
work\@b@c@d_to_7segment
work\@b@c@d_to_7segment\_primary.dat
work\@b@c@d_to_7segment\_primary.dbs
work\@b@c@d_to_7segment\_primary.vhd
work\@b@c@d_to_7segment\verilog.prw
work\@b@c@d_to_7segment\verilog.psm
work\@l@a@b05
work\@l@a@b05\_primary.dat
work\@l@a@b05\_primary.dbs
work\@l@a@b05\_primary.vhd
work\@l@a@b05\verilog.prw
work\@l@a@b05\verilog.psm
work\@seven@seg_@c@t@r@l
work\@seven@seg_@c@t@r@l\_primary.dat
work\@seven@seg_@c@t@r@l\_primary.dbs
work\@seven@seg_@c@t@r@l\_primary.vhd
work\@seven@seg_@c@t@r@l\verilog.prw
work\@seven@seg_@c@t@r@l\verilog.psm
work\_info
work\_temp
work\_vmake
work\binary_to_@b@c@d
work\binary_to_@b@c@d\_primary.dat
work\binary_to_@b@c@d\_primary.dbs
work\binary_to_@b@c@d\_primary.vhd
work\binary_to_@b@c@d\verilog.prw
work\binary_to_@b@c@d\verilog.psm
work\linedecoder
work\linedecoder\_primary.dat
work\linedecoder\_primary.dbs
work\linedecoder\_primary.vhd
work\linedecoder\verilog.prw
work\linedecoder\verilog.psm