文件名称:bingo_spi_test
- 所属分类：
- 书籍源码
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2017-09-25
- 文件大小：
- 52kb
- 下载次数：
- 0次
- 提 供 者：
- Augus******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
利用SPI实现FPGA和外设之间的通信。经过Modelsim仿真验证。（为FPGA设计技巧与案例开发详解一书源码）(Using SPI to implement communication between FPGA and peripheral. After Modelsim simulation verification. (for FPGA design techniques and case development detailed explanation of a book source))
相关搜索： verilog/SPI通信
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下载文件列表
bingo_spi_test\design\pll_system_ctrl.v
bingo_spi_test\design\spi_receicer.v
bingo_spi_test\design\spi_transfer.v
bingo_spi_test\design\system_init_delay.v
bingo_spi_test\sim\run .do
bingo_spi_test\sim\tb_spi_receiver.cr.mti
bingo_spi_test\sim\tb_spi_receiver.mpf
bingo_spi_test\sim\tb_spi_receiver.v
bingo_spi_test\sim\vsim.wlf
bingo_spi_test\sim\work\spi_receiver\verilog.asm64
bingo_spi_test\sim\work\spi_receiver\verilog.rw64
bingo_spi_test\sim\work\spi_receiver\_primary.dat
bingo_spi_test\sim\work\spi_receiver\_primary.dbs
bingo_spi_test\sim\work\spi_receiver\_primary.vhd
bingo_spi_test\sim\work\spi_transfer\verilog.asm64
bingo_spi_test\sim\work\spi_transfer\verilog.rw64
bingo_spi_test\sim\work\spi_transfer\_primary.dat
bingo_spi_test\sim\work\spi_transfer\_primary.dbs
bingo_spi_test\sim\work\spi_transfer\_primary.vhd
bingo_spi_test\sim\work\tb_spi_receiver\verilog.asm64
bingo_spi_test\sim\work\tb_spi_receiver\verilog.rw64
bingo_spi_test\sim\work\tb_spi_receiver\_primary.dat
bingo_spi_test\sim\work\tb_spi_receiver\_primary.dbs
bingo_spi_test\sim\work\tb_spi_receiver\_primary.vhd
bingo_spi_test\sim\work\_info
bingo_spi_test\sim\work\_temp\vlog1ndadr
bingo_spi_test\sim\work\_temp\vlog3yiawb
bingo_spi_test\sim\work\_temp\vlog98w4gz
bingo_spi_test\sim\work\_vmake
bingo_spi_test\sim\work\spi_receiver
bingo_spi_test\sim\work\spi_transfer
bingo_spi_test\sim\work\tb_spi_receiver
bingo_spi_test\sim\work\_temp
bingo_spi_test\sim\work
bingo_spi_test\design
bingo_spi_test\docunment
bingo_spi_test\quartus_prj
bingo_spi_test\sim
bingo_spi_test
bingo_spi_test\design\spi_receicer.v
bingo_spi_test\design\spi_transfer.v
bingo_spi_test\design\system_init_delay.v
bingo_spi_test\sim\run .do
bingo_spi_test\sim\tb_spi_receiver.cr.mti
bingo_spi_test\sim\tb_spi_receiver.mpf
bingo_spi_test\sim\tb_spi_receiver.v
bingo_spi_test\sim\vsim.wlf
bingo_spi_test\sim\work\spi_receiver\verilog.asm64
bingo_spi_test\sim\work\spi_receiver\verilog.rw64
bingo_spi_test\sim\work\spi_receiver\_primary.dat
bingo_spi_test\sim\work\spi_receiver\_primary.dbs
bingo_spi_test\sim\work\spi_receiver\_primary.vhd
bingo_spi_test\sim\work\spi_transfer\verilog.asm64
bingo_spi_test\sim\work\spi_transfer\verilog.rw64
bingo_spi_test\sim\work\spi_transfer\_primary.dat
bingo_spi_test\sim\work\spi_transfer\_primary.dbs
bingo_spi_test\sim\work\spi_transfer\_primary.vhd
bingo_spi_test\sim\work\tb_spi_receiver\verilog.asm64
bingo_spi_test\sim\work\tb_spi_receiver\verilog.rw64
bingo_spi_test\sim\work\tb_spi_receiver\_primary.dat
bingo_spi_test\sim\work\tb_spi_receiver\_primary.dbs
bingo_spi_test\sim\work\tb_spi_receiver\_primary.vhd
bingo_spi_test\sim\work\_info
bingo_spi_test\sim\work\_temp\vlog1ndadr
bingo_spi_test\sim\work\_temp\vlog3yiawb
bingo_spi_test\sim\work\_temp\vlog98w4gz
bingo_spi_test\sim\work\_vmake
bingo_spi_test\sim\work\spi_receiver
bingo_spi_test\sim\work\spi_transfer
bingo_spi_test\sim\work\tb_spi_receiver
bingo_spi_test\sim\work\_temp
bingo_spi_test\sim\work
bingo_spi_test\design
bingo_spi_test\docunment
bingo_spi_test\quartus_prj
bingo_spi_test\sim
bingo_spi_test