文件名称:ModelSim
介绍说明－－下载内容均来自于网络，请自行研究使用
Implementing a full adder in ModelSim by using Verilog Language
相关搜索： verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
lab 2
lab 2\lab2_task.cr.mti
lab 2\lab2_task.mpf
lab 2\tasks.v
lab 2\TB_Tasks.v
lab 2\vsim.wlf
lab 2\work
lab 2\work\@f@a
lab 2\work\@f@a\verilog.asm
lab 2\work\@f@a\_primary.dat
lab 2\work\@f@a\_primary.vhd
lab 2\work\add4bit
lab 2\work\add4bit\verilog.asm
lab 2\work\add4bit\_primary.dat
lab 2\work\add4bit\_primary.vhd
lab 2\work\mux4to1
lab 2\work\mux4to1\verilog.asm
lab 2\work\mux4to1\_primary.dat
lab 2\work\mux4to1\_primary.vhd
lab 2\work\mux8to1
lab 2\work\mux8to1\verilog.asm
lab 2\work\mux8to1\_primary.dat
lab 2\work\mux8to1\_primary.vhd
lab 2\work\mux_8to1
lab 2\work\mux_8to1\verilog.asm
lab 2\work\mux_8to1\_primary.dat
lab 2\work\mux_8to1\_primary.vhd
lab 2\work\stimulus
lab 2\work\stimulus\verilog.asm
lab 2\work\stimulus\_primary.dat
lab 2\work\stimulus\_primary.vhd
lab 2\work\tb_mux4t01
lab 2\work\tb_mux4t01\verilog.asm
lab 2\work\tb_mux4t01\_primary.dat
lab 2\work\tb_mux4t01\_primary.vhd
lab 2\work\_info
lab 2\~$lab 2.docx
lab 2\lab2_task.cr.mti
lab 2\lab2_task.mpf
lab 2\tasks.v
lab 2\TB_Tasks.v
lab 2\vsim.wlf
lab 2\work
lab 2\work\@f@a
lab 2\work\@f@a\verilog.asm
lab 2\work\@f@a\_primary.dat
lab 2\work\@f@a\_primary.vhd
lab 2\work\add4bit
lab 2\work\add4bit\verilog.asm
lab 2\work\add4bit\_primary.dat
lab 2\work\add4bit\_primary.vhd
lab 2\work\mux4to1
lab 2\work\mux4to1\verilog.asm
lab 2\work\mux4to1\_primary.dat
lab 2\work\mux4to1\_primary.vhd
lab 2\work\mux8to1
lab 2\work\mux8to1\verilog.asm
lab 2\work\mux8to1\_primary.dat
lab 2\work\mux8to1\_primary.vhd
lab 2\work\mux_8to1
lab 2\work\mux_8to1\verilog.asm
lab 2\work\mux_8to1\_primary.dat
lab 2\work\mux_8to1\_primary.vhd
lab 2\work\stimulus
lab 2\work\stimulus\verilog.asm
lab 2\work\stimulus\_primary.dat
lab 2\work\stimulus\_primary.vhd
lab 2\work\tb_mux4t01
lab 2\work\tb_mux4t01\verilog.asm
lab 2\work\tb_mux4t01\_primary.dat
lab 2\work\tb_mux4t01\_primary.vhd
lab 2\work\_info
lab 2\~$lab 2.docx