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文件名称:FPGA 2017.08.18

  • 所属分类：
  • 其他小程序
  • 资源属性：
  • [VHDL] [源码]
  • 上传时间：
  • 2017-08-18
  • 文件大小：
  • 9.21mb
  • 下载次数：
  • 1次
  • 提 供 者：
  • Scrip*****
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

实现步进电机驱动+加减速控制+编码器检验。(Stepper motor drive + acceleration and deceleration control + encoder test.)
相关搜索： 步进电机驱动
加减速控制

(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA\DYY_FPGA\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf

FPGA\DYY_FPGA\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.sdb

FPGA\DYY_FPGA\component\work\DESIGN_IO\DESIGN_IO.cxf

FPGA\DYY_FPGA\component\work\DESIGN_IO\DESIGN_IO.sdb

FPGA\DYY_FPGA\component\work\toplayer\datasheet.xsl

FPGA\DYY_FPGA\component\work\toplayer\drcss.xsl

FPGA\DYY_FPGA\component\work\toplayer\toplayer.cxf

FPGA\DYY_FPGA\component\work\toplayer\toplayer.pdc

FPGA\DYY_FPGA\component\work\toplayer\toplayer.sdb

FPGA\DYY_FPGA\component\work\toplayer\toplayer.v

FPGA\DYY_FPGA\component\work\toplayer\toplayer_DataSheet.xml

FPGA\DYY_FPGA\component\work\toplayer\toplayer_DRC.xml

FPGA\DYY_FPGA\component\work\toplayer\toplayer_manifest.txt

FPGA\DYY_FPGA\designer\impl1\ada00616-1.tmp

FPGA\DYY_FPGA\designer\impl1\ada08188-1.tmp

FPGA\DYY_FPGA\designer\impl1\coords.adb

FPGA\DYY_FPGA\designer\impl1\coords.ide_des

FPGA\DYY_FPGA\designer\impl1\coords.tcl

FPGA\DYY_FPGA\designer\impl1\coords_compile_log.rpt

FPGA\DYY_FPGA\designer\impl1\coords_compile_report.txt

FPGA\DYY_FPGA\designer\impl1\coords_report_pin_byname.txt

FPGA\DYY_FPGA\designer\impl1\coords_report_pin_bynumber.txt

FPGA\DYY_FPGA\designer\impl1\run_designer_tool.log

FPGA\DYY_FPGA\designer\impl1\run_designer_tool.tcl

FPGA\DYY_FPGA\designer\impl1\run_pinrpt.tcl

FPGA\DYY_FPGA\designer\impl1\toplayer.adb

FPGA\DYY_FPGA\designer\impl1\toplayer.dtf\verify.log

FPGA\DYY_FPGA\designer\impl1\toplayer.ide_des

FPGA\DYY_FPGA\designer\impl1\toplayer.pdb

FPGA\DYY_FPGA\designer\impl1\toplayer.pdb.depends

FPGA\DYY_FPGA\designer\impl1\toplayer.plk

FPGA\DYY_FPGA\designer\impl1\toplayer.tcl

FPGA\DYY_FPGA\designer\impl1\toplayer_compile_log.rpt

FPGA\DYY_FPGA\designer\impl1\toplayer_compile_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_fp\$$FlashPro_08929.L$$

FPGA\DYY_FPGA\designer\impl1\toplayer_fp\fpalgo_1.salg

FPGA\DYY_FPGA\designer\impl1\toplayer_fp\projectData\toplayer.pdb

FPGA\DYY_FPGA\designer\impl1\toplayer_fp\projectData\toplayer.plk

FPGA\DYY_FPGA\designer\impl1\toplayer_fp\toplayer.pro

FPGA\DYY_FPGA\designer\impl1\toplayer_fp\toplayer.tcl

FPGA\DYY_FPGA\designer\impl1\toplayer_fp\toplayer_program.log

FPGA\DYY_FPGA\designer\impl1\toplayer_fp.tcl

FPGA\DYY_FPGA\designer\impl1\toplayer_globalnet_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_globalusage_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_iobank_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_maxdelay_timingviolations_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_maxdelay_timing_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_mindelay_timingviolations_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_mindelay_timing_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_placeroute_log.rpt

FPGA\DYY_FPGA\designer\impl1\toplayer_place_and_route_report.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_prgdata_log.rpt

FPGA\DYY_FPGA\designer\impl1\toplayer_report_pin_byname.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_report_pin_bynumber.txt

FPGA\DYY_FPGA\designer\impl1\toplayer_verifytiming_log.rpt

FPGA\DYY_FPGA\DYY_FPGA.prjx

FPGA\DYY_FPGA\hdl\coords.v

FPGA\DYY_FPGA\hdl\decode.v

FPGA\DYY_FPGA\hdl\driver.v

FPGA\DYY_FPGA\hdl\dw_filter.v

FPGA\DYY_FPGA\hdl\logic.v

FPGA\DYY_FPGA\hdl\power_on_rst.v

FPGA\DYY_FPGA\hdl\read_coord.v

FPGA\DYY_FPGA\hdl\reg16_h.v

FPGA\DYY_FPGA\hdl\speed.v

FPGA\DYY_FPGA\simulation\modelsim.ini

FPGA\DYY_FPGA\simulation\modelsim.ini.sav

FPGA\DYY_FPGA\smartgen\DESIGN_FIRMWARE_work.ixf

FPGA\DYY_FPGA\smartgen\DESIGN_IO_work.ixf

FPGA\DYY_FPGA\smartgen\reg16\reg16.cxf

FPGA\DYY_FPGA\smartgen\reg16\reg16.gen

FPGA\DYY_FPGA\smartgen\reg16\reg16.log

FPGA\DYY_FPGA\smartgen\reg16\reg16.v

FPGA\DYY_FPGA\smartgen\reg16_work.ixf

FPGA\DYY_FPGA\smartgen\smartgen.aws

FPGA\DYY_FPGA\smartgen\toplayer_work.ixf

FPGA\DYY_FPGA\synthesis\.recordref_modgen

FPGA\DYY_FPGA\synthesis\add__const_cin_w16.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w16_0.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w16_2.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w16_3.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w17.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w17_0.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w17_1.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w17_2.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w17_3.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w17_4.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w17_5.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w17_6.fdepxmr

FPGA\DYY_FPGA\synthesis\add__const_cin_w32.fdepxmr

FPGA\DYY_FPGA\synthesis\backup\coords.srr

FPGA\DYY_FPGA\synthesis\backup\toplayer.srr

FPGA\DYY_FPGA\synthesis\coords.areasrr

FPGA\DYY_FPGA\synthesis\coords.edn

FPGA\DYY_FPGA\synthesis\coords.fse

FPGA\DYY_FPGA\synthesis\coords.htm

FPGA\DYY_FPGA\synthesis\coords.map

FPGA\DYY_FPGA\synthesis\coords.pdc

FPGA\DYY_FPGA\synthesis\coords.sap

FPGA\DYY_FPGA\synthesis\coords.sdf

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