文件名称:Abspeecessing
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A fast connected component labeling algorithm based on FPGA is presented for high speed image processing
on the condition that the images are continuous without horizontal blanking. Using run length code to optimize image
labeling, the labels’number and length of equivalent table can be reduced. And the component’s features can also be
extracted during run length coding. Then using the way of scanning every pixel, the connected labels can be linked in a
single clock period. Finally the labels and features are merged in the procedure of equivalent table combination. The FPGA
simulation results indicate that, when connected component labeling and features extraction for a continuous binary image
are in progress, the processing time just includes the image input time and the equivalents table combination time. It is
more efficient than others and suitable for fast image recognition and tracking
on the condition that the images are continuous without horizontal blanking. Using run length code to optimize image
labeling, the labels’number and length of equivalent table can be reduced. And the component’s features can also be
extracted during run length coding. Then using the way of scanning every pixel, the connected labels can be linked in a
single clock period. Finally the labels and features are merged in the procedure of equivalent table combination. The FPGA
simulation results indicate that, when connected component labeling and features extraction for a continuous binary image
are in progress, the processing time just includes the image input time and the equivalents table combination time. It is
more efficient than others and suitable for fast image recognition and tracking
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