文件名称:project_fir_test

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Linux] [SHELL] [源码]
  • 上传时间:
  • 2017-04-17
  • 文件大小:
  • 37.35mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • k**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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基于verilog的FIR滤波器设计,使用BASYS3作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
(系统自动生成,下载前可以参看下载内容)

下载文件列表





project_fir_test\c1.coe

................\c2.coe

................\data.coe

................\project_fir_test.cache\wt\java_command_handlers.wdf

................\......................\..\synthesis.wdf

................\......................\..\synthesis_details.wdf

................\......................\..\webtalk_pa.xml

................\......................\..\xsim.wdf

................\.................hw\project_fir_test.lpr

................\...................\webtalk\.xsim_webtallk.info

................\.................runs\.jobs\vrs_config_1.xml

................\.....................\.....\vrs_config_10.xml

................\.....................\.....\vrs_config_11.xml

................\.....................\.....\vrs_config_12.xml

................\.....................\.....\vrs_config_13.xml

................\.....................\.....\vrs_config_14.xml

................\.....................\.....\vrs_config_15.xml

................\.....................\.....\vrs_config_16.xml

................\.....................\.....\vrs_config_17.xml

................\.....................\.....\vrs_config_18.xml

................\.....................\.....\vrs_config_19.xml

................\.....................\.....\vrs_config_2.xml

................\.....................\.....\vrs_config_20.xml

................\.....................\.....\vrs_config_21.xml

................\.....................\.....\vrs_config_22.xml

................\.....................\.....\vrs_config_23.xml

................\.....................\.....\vrs_config_24.xml

................\.....................\.....\vrs_config_25.xml

................\.....................\.....\vrs_config_26.xml

................\.....................\.....\vrs_config_27.xml

................\.....................\.....\vrs_config_28.xml

................\.....................\.....\vrs_config_3.xml

................\.....................\.....\vrs_config_4.xml

................\.....................\.....\vrs_config_5.xml

................\.....................\.....\vrs_config_6.xml

................\.....................\.....\vrs_config_7.xml

................\.....................\.....\vrs_config_8.xml

................\.....................\.....\vrs_config_9.xml

................\.....................\blk_mem_gen_0_synth_1\.vivado.begin.rst

................\.....................\.....................\.vivado.end.rst

................\.....................\.....................\.Vivado_Synthesis.queue.rst

................\.....................\.....................\blk_mem_gen_0.dcp

................\.....................\.....................\blk_mem_gen_0.tcl

................\.....................\.....................\blk_mem_gen_0.vds

................\.....................\.....................\blk_mem_gen_0_utilization_synth.pb

................\.....................\.....................\blk_mem_gen_0_utilization_synth.rpt

................\.....................\.....................\gen_run.xml

................\.....................\.....................\htr.txt

................\.....................\.....................\ISEWrap.js

................\.....................\.....................\ISEWrap.sh

................\.....................\.....................\project.wdf

................\.....................\.....................\rundef.js

................\.....................\.....................\runme.bat

................\.....................\.....................\runme.log

................\.....................\.....................\runme.sh

................\.....................\.....................\vivado.jou

................\.....................\.....................\vivado.pb

................\.....................\dds_highf_synth_1\.vivado.begin.rst

................\.....................\.................\.vivado.end.rst

................\.....................\.................\.Vivado_Synthesis.queue.rst

................\.....................\.................\dds_highf.dcp

................\.....................\.................\dds_highf.tcl

....

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