文件名称:stm32-and-fpga-communication-by-spi

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2017-02-26
  • 文件大小:
  • 3mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 张*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

该实验完成的功能是STM32与FPGA通信-The function of the experiment is STM32 and FPGA communication
(系统自动生成,下载前可以参看下载内容)

下载文件列表





spi\data_src.v

...\data_src.v.bak

...\.b\logic_util_heursitic.dat

...\..\pll_8_50M_altpll.v

...\..\prev_cmp_STM32_FPGA_SPI.qmsg

...\..\STM32_FPGA_SPI.amm.cdb

...\..\STM32_FPGA_SPI.asm.qmsg

...\..\STM32_FPGA_SPI.asm.rdb

...\..\STM32_FPGA_SPI.cbx.xml

...\..\STM32_FPGA_SPI.cmp.bpm

...\..\STM32_FPGA_SPI.cmp.cbp

...\..\STM32_FPGA_SPI.cmp.cdb

...\..\STM32_FPGA_SPI.cmp.hdb

...\..\STM32_FPGA_SPI.cmp.kpt

...\..\STM32_FPGA_SPI.cmp.logdb

...\..\STM32_FPGA_SPI.cmp.rdb

...\..\STM32_FPGA_SPI.cmp.tdb

...\..\STM32_FPGA_SPI.cmp0.ddb

...\..\STM32_FPGA_SPI.cmp_merge.kpt

...\..\STM32_FPGA_SPI.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

...\..\STM32_FPGA_SPI.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd

...\..\STM32_FPGA_SPI.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd

...\..\STM32_FPGA_SPI.db_info

...\..\STM32_FPGA_SPI.eda.qmsg

...\..\STM32_FPGA_SPI.fit.qmsg

...\..\STM32_FPGA_SPI.hier_info

...\..\STM32_FPGA_SPI.hif

...\..\STM32_FPGA_SPI.idb.cdb

...\..\STM32_FPGA_SPI.lpc.html

...\..\STM32_FPGA_SPI.lpc.rdb

...\..\STM32_FPGA_SPI.lpc.txt

...\..\STM32_FPGA_SPI.map.bpm

...\..\STM32_FPGA_SPI.map.cbp

...\..\STM32_FPGA_SPI.map.cdb

...\..\STM32_FPGA_SPI.map.hdb

...\..\STM32_FPGA_SPI.map.kpt

...\..\STM32_FPGA_SPI.map.logdb

...\..\STM32_FPGA_SPI.map.qmsg

...\..\STM32_FPGA_SPI.map_bb.cdb

...\..\STM32_FPGA_SPI.map_bb.hdb

...\..\STM32_FPGA_SPI.map_bb.logdb

...\..\STM32_FPGA_SPI.pre_map.cdb

...\..\STM32_FPGA_SPI.pre_map.hdb

...\..\STM32_FPGA_SPI.rpp.qmsg

...\..\STM32_FPGA_SPI.rtlv.hdb

...\..\STM32_FPGA_SPI.rtlv_sg.cdb

...\..\STM32_FPGA_SPI.rtlv_sg_swap.cdb

...\..\STM32_FPGA_SPI.sgate.rvd

...\..\STM32_FPGA_SPI.sgate_sm.rvd

...\..\STM32_FPGA_SPI.sgdiff.cdb

...\..\STM32_FPGA_SPI.sgdiff.hdb

...\..\STM32_FPGA_SPI.sld_design_entry.sci

...\..\STM32_FPGA_SPI.sld_design_entry_dsc.sci

...\..\STM32_FPGA_SPI.smart_action.txt

...\..\STM32_FPGA_SPI.smp_dump.txt

...\..\STM32_FPGA_SPI.sta.qmsg

...\..\STM32_FPGA_SPI.sta.rdb

...\..\STM32_FPGA_SPI.syn_hier_info

...\..\STM32_FPGA_SPI.tan.qmsg

...\..\STM32_FPGA_SPI.tiscmp.fastest_slow_1200mv_0c.ddb

...\..\STM32_FPGA_SPI.tiscmp.fastest_slow_1200mv_85c.ddb

...\..\STM32_FPGA_SPI.tis_db_list.ddb

...\..\STM32_FPGA_SPI.tmw_info

...\greybox_tmp\cbx_args.txt

...\incremental_db\compiled_partitions\STM32_FPGA_SPI.db_info

...\..............\...................\STM32_FPGA_SPI.root_partition.cmp.cdb

...\..............\...................\STM32_FPGA_SPI.root_partition.cmp.dfp

...\..............\...................\STM32_FPGA_SPI.root_partition.cmp.hdb

...\..............\...................\STM32_FPGA_SPI.root_partition.cmp.kpt

...\..............\...................\STM32_FPGA_SPI.root_partition.cmp.logdb

...\..............\...................\STM32_FPGA_SPI.root_partition.cmp.rcfdb

...\..............\...................\STM32_FPGA_SPI.root_partition.cmp.re.rcfdb

...\..............\...................\STM32_FPGA_SPI.root_partition.hbdb.cdb

...\..............\...................\STM32_FPGA_SPI.root_partition.map.cdb

...\..............\...................\STM32_FPGA_SPI.root_partition.map.dpi

...\..............\...................\STM32_FPGA_SPI.root_partition.map.hdb

...\..............\...................\STM32_FPGA_SPI.root_partition.map.kpt

...\..............\README

...\output_file.map

...\PLLJ_PLLSPE_INFO.txt

...\pll_50M.ppf

...\pll_50M.qip

...\pll_50M.v

...\pll_50M_bb.v

...\pll_50M_inst.v

...\pll_clk.v

...\pll_clk.v.bak

...\simulation\modelsim\modelsim.ini

...\..........\........\msim_transcript

...\..........\........\rtl_work\@s@t@m32_@f@p@g@a_@s@p@i\verilog.prw

...\..........\........\........\........................\verilog.psm

...\..........\........\........\........................\_primary.dat

...\..........\........\........\........................\_primary.dbs

...\..........\........\........\........................\_primary.vhd

...\..........\........\........\........................_vlg_tst\verilog.prw

...\..........\........\........\................................\verilog.psm

...\..........\........\........\................................\_primary.dat

...\..........\........\........\...........

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