文件名称:last
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verilog，FPGA的TDC电路设计-verilog ，TDC base on FPGA
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下载文件列表
last
....\_ngo
....\....\netlist.lst
....\_xmsgs
....\......\bitgen.xmsgs
....\......\map.xmsgs
....\......\netgen.xmsgs
....\......\ngdbuild.xmsgs
....\......\par.xmsgs
....\......\trce.xmsgs
....\......\xst.xmsgs
....\device_usage_statistics.html
....\la.nmc
....\la_fpga_editor.log
....\last.bgn
....\last.bit
....\last.bld
....\last.cel
....\last.cmd_log
....\last.cr.mti
....\last.drc
....\last.ise
....\last.ise_ISE_Backup
....\last.lso
....\last.mpf
....\last.ncd
....\last.ngc
....\last.ngd
....\last.ngr
....\last.ntrc_log
....\last.pad
....\last.par
....\last.pcf
....\last.prj
....\last.stx
....\last.syr
....\last.twr
....\last.twx
....\last.ucf
....\last.unroutes
....\last.ut
....\last.v
....\last.xpi
....\last.xst
....\last_fpga_editor.log
....\last_guide.ncd
....\last_map.map
....\last_map.mrp
....\last_map.ncd
....\last_map.ngm
....\last_pad.csv
....\last_pad.txt
....\last_prev_built.ngd
....\last_summary.html
....\last_summary.xml
....\last_usage.xml
....\llast.cr.mti
....\llast.mpf
....\netgen
....\......\par
....\......\...\last_timesim.nlf
....\......\...\last_timesim.sdf
....\......\...\last_timesim.v
....\tb.ant
....\tb.jhd
....\tb.tbw
....\tb.tfw
....\tb.tfw.bak
....\tb.xwv
....\tb.xwv_bak
....\tb_bencher.prj
....\vsim.wlf
....\wlft0e21m5
....\wlft1t2ce8
....\wlft6307c3
....\wlftac0fni
....\wlftfjqak3
....\wlftmbkhaj
....\wlftrwyin4
....\wlftw0hwtz
....\wlftxej53n
....\work
....\....\@_opt
....\....\.....\__sdf1
....\....\.....\__sdf2
....\....\.....\_deps
....\....\.....\vopt005wqq
....\....\.....\vopt03qw7y
....\....\.....\vopt076q5z
....\....\.....\vopt099w3z
....\....\.....\vopt0f3srq
....\....\.....\vopt0n6zgs
....\....\.....\vopt0r7s4z
....\....\.....\vopt0s7sv2
....\....\.....\vopt1afyix
....\....\.....\vopt1b96vg
....\....\.....\vopt1di481
....\....\.....\vopt1g94nq
....\....\.....\vopt1gi1wy
....\....\.....\vopt1vg1ix