文件名称:cachecontroller_latest.tar
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This project is to develop a direct mapped cache controller for embedded applications.
Key Design Features
- Direct mapped with configurable address size, line size and number of cache lines
- Non Pipelined architecture
- No Cache flush
Synthesis will be conducted using VirtexII Pro
Key Design Features
- Direct mapped with configurable address size, line size and number of cache lines
- Non Pipelined architecture
- No Cache flush
Synthesis will be conducted using VirtexII Pro
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117143163cachecontroller_latest.tar