文件名称:FPGA_JOW
介绍说明－－下载内容均来自于网络，请自行研究使用
本设计为学校打铃管理系统，使用VHDL设计，根据打铃功能不同输出不同的音乐,工作模式包括正常上课模式、考试模式、放假模式-The design management system for the school bell, the use of VHDL to design, according to different output different music in Bell functions, working modes including normal class mode, test mode, the holiday mode
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA_JOW
........\db
........\..\altsyncram_6e01.tdf
........\..\FPGA_JOW.asm.qmsg
........\..\FPGA_JOW.asm_labs.ddb
........\..\FPGA_JOW.cbx.xml
........\..\FPGA_JOW.cmp.bpm
........\..\FPGA_JOW.cmp.cdb
........\..\FPGA_JOW.cmp.ecobp
........\..\FPGA_JOW.cmp.hdb
........\..\FPGA_JOW.cmp.kpt
........\..\FPGA_JOW.cmp.logdb
........\..\FPGA_JOW.cmp.rdb
........\..\FPGA_JOW.cmp.tdb
........\..\FPGA_JOW.cmp0.ddb
........\..\FPGA_JOW.cmp2.ddb
........\..\FPGA_JOW.cmp_merge.kpt
........\..\FPGA_JOW.db_info
........\..\FPGA_JOW.eco.cdb
........\..\FPGA_JOW.eds_overflow
........\..\FPGA_JOW.fit.qmsg
........\..\FPGA_JOW.fnsim.cdb
........\..\FPGA_JOW.fnsim.hdb
........\..\FPGA_JOW.fnsim.qmsg
........\..\FPGA_JOW.FPGA_JOW0.rtl.mif
........\..\FPGA_JOW.hier_info
........\..\FPGA_JOW.hif
........\..\FPGA_JOW.lpc.html
........\..\FPGA_JOW.lpc.rdb
........\..\FPGA_JOW.lpc.txt
........\..\FPGA_JOW.map.bpm
........\..\FPGA_JOW.map.cdb
........\..\FPGA_JOW.map.ecobp
........\..\FPGA_JOW.map.hdb
........\..\FPGA_JOW.map.kpt
........\..\FPGA_JOW.map.logdb
........\..\FPGA_JOW.map.qmsg
........\..\FPGA_JOW.map_bb.cdb
........\..\FPGA_JOW.map_bb.hdb
........\..\FPGA_JOW.map_bb.logdb
........\..\FPGA_JOW.pre_map.cdb
........\..\FPGA_JOW.pre_map.hdb
........\..\FPGA_JOW.rtlv.hdb
........\..\FPGA_JOW.rtlv_sg.cdb
........\..\FPGA_JOW.rtlv_sg_swap.cdb
........\..\FPGA_JOW.sgdiff.cdb
........\..\FPGA_JOW.sgdiff.hdb
........\..\FPGA_JOW.sim.cvwf
........\..\FPGA_JOW.sim.hdb
........\..\FPGA_JOW.sim.qmsg
........\..\FPGA_JOW.sim.rdb
........\..\FPGA_JOW.simfam
........\..\FPGA_JOW.sim_temp_.vwf
........\..\FPGA_JOW.sld_design_entry.sci
........\..\FPGA_JOW.sld_design_entry_dsc.sci
........\..\FPGA_JOW.syn_hier_info
........\..\FPGA_JOW.tan.qmsg
........\..\FPGA_JOW.tis_db_list.ddb
........\..\FPGA_JOW.tmw_info
........\..\FPGA_JOW_global_asgn_op.abo
........\..\mux_3nc.tdf
........\..\mux_dqc.tdf
........\..\mux_joc.tdf
........\..\prev_cmp_FPGA_JOW.map.qmsg
........\..\prev_cmp_FPGA_JOW.qmsg
........\..\prev_cmp_FPGA_JOW.sim.qmsg
........\..\wed.wsf
........\drive.bsf
........\drive.vhd
........\drive.vhd.bak
........\FPGA_JOW.asm.rpt
........\FPGA_JOW.done
........\FPGA_JOW.fit.rpt
........\FPGA_JOW.fit.smsg
........\FPGA_JOW.fit.summary
........\FPGA_JOW.flow.rpt
........\FPGA_JOW.map.rpt
........\FPGA_JOW.map.summary
........\FPGA_JOW.pin
........\FPGA_JOW.pof
........\FPGA_JOW.qpf
........\FPGA_JOW.qsf
........\FPGA_JOW.qws
........\FPGA_JOW.sim.rpt
........\FPGA_JOW.sof
........\FPGA_JOW.tan.rpt
........\FPGA_JOW.tan.summary
........\FPGA_JOW.vwf
........\hadapt.bsf
........\hour1.bsf
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\FPGA_JOW.root_partition.cmp.atm
........\..............\...................\FPGA_JOW.root_partition.cmp.dfp
........\..............\...................\FPGA_JOW.root_partition.cmp.hdbx
........\..............\...................\FPGA_JOW.root_partition.cmp.kpt
........\..............\...................\FPGA_JOW.root_partition.cmp.logdb
........\..............\...................\FPGA_JOW.root_partition.cmp.rcf
........\..............\...................\FPGA_JOW.root_partition.map.atm
........\..............\...................\FPGA_JOW.root_partition.map.dpi