文件名称:ethernet
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opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。-Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim.
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下载文件列表
ethernet
........\CVS
........\...\Entries
........\...\Entries.Log
........\...\Repository
........\...\Root
........\...\Template
........\README.txt
........\bench
........\.....\CVS
........\.....\...\Entries
........\.....\...\Entries.Log
........\.....\...\Repository
........\.....\...\Root
........\.....\...\Template
........\.....\verilog
........\.....\.......\CVS
........\.....\.......\...\Entries
........\.....\.......\...\Repository
........\.....\.......\...\Root
........\.....\.......\...\Template
........\.....\.......\eth_host.v
........\.....\.......\eth_memory.v
........\.....\.......\eth_phy.v
........\.....\.......\eth_phy_defines.v
........\.....\.......\tb_cop.v
........\.....\.......\tb_eth_defines.v
........\.....\.......\tb_eth_top.v
........\.....\.......\tb_ethernet.v
........\.....\.......\tb_ethernet_with_cop.v
........\.....\.......\wb_bus_mon.v
........\.....\.......\wb_master32.v
........\.....\.......\wb_master_behavioral.v
........\.....\.......\wb_model_defines.v
........\.....\.......\wb_slave_behavioral.v
........\doc
........\...\CVS
........\...\...\Entries
........\...\...\Entries.Log
........\...\...\Repository
........\...\...\Root
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........\...\eth_design_document.pdf
........\...\eth_speci.pdf
........\...\ethernet_datasheet_OC_head.pdf
........\...\ethernet_product_brief_OC_head.pdf
........\...\src
........\...\...\CVS
........\...\...\...\Entries
........\...\...\...\Repository
........\...\...\...\Root
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........\...\...\eth_design_document.doc
........\...\...\eth_speci.doc
........\...\...\ethernet_datasheet_OC_head.doc
........\...\...\ethernet_product_brief_OC_head.doc
........\rtl
........\...\CVS
........\...\...\Entries
........\...\...\Entries.Log
........\...\...\Repository
........\...\...\Root
........\...\...\Template
........\...\verilog
........\...\.......\BUGS
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\...\Template
........\...\.......\TODO
........\...\.......\eth_clockgen.v
........\...\.......\eth_cop.v
........\...\.......\eth_crc.v
........\...\.......\eth_defines.v
........\...\.......\eth_fifo.v
........\...\.......\eth_maccontrol.v
........\...\.......\eth_macstatus.v
........\...\.......\eth_miim.v
........\...\.......\eth_outputcontrol.v
........\...\.......\eth_random.v
........\...\.......\eth_receivecontrol.v
........\...\.......\eth_register.v
........\...\.......\eth_registers.v
........\...\.......\eth_rxaddrcheck.v
........\...\.......\eth_rxcounters.v
........\...\.......\eth_rxethmac.v
........\...\.......\eth_rxstatem.v
........\...\.......\eth_shiftreg.v
........\...\.......\eth_spram_256x32.v
........\...\.......\eth_top.v
........\...\.......\eth_transmitcontrol.v
........\...\.......\eth_txcounters.v
........\...\.......\eth_txethmac.v
........\...\.......\eth_txstatem.v
........\...\.......\eth_wishbone.v
........\...\.......\timescale.v
........\...\.......\xilinx_dist_ram_16x32.v
........\sim
........\...\CVS