文件名称:DigitalCompinacijaSimulacija
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
It is a bridge between CPU and sensors where user can not connect sensors directly on CPU. It consumes very small number od LUTs and it is suitable for CPLD design. it works on following way, when logic detects falling edge of RX, then this action triggers other logic and then starts sending data on TX line-It is a bridge between CPU and sensors where user can not connect sensors directly on CPU. It consumes very small number od LUTs and it is suitable for CPLD design. it works on following way, when logic detects falling edge of RX, then this action triggers other logic and then starts sending data on TX line
(系统自动生成,下载前可以参看下载内容)
下载文件列表
BR_GENERATOR.vhd
clkAdder.vhd
edgeDetector.vhd
HalfAdder.vhd
logicPkg.vhd
TX_modul.vhd