文件名称:0003__10.1049@iet-cds.2013.0097
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This study presents a parallel very large scale integrated circuits architecture for an intra-predictor based on a fast 4 × 4
algorithm. For real-time scheduling, the proposed algorithm overcomes the data dependency between intra-prediction and intracoding,
thereby improving coding performance and reducing the number of coding cycles.
algorithm. For real-time scheduling, the proposed algorithm overcomes the data dependency between intra-prediction and intracoding,
thereby improving coding performance and reducing the number of coding cycles.
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0003__10.1049@iet-cds.2013.0097.pdf