文件名称:DDS_FPGA
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任意波形发生器FPGA实现，Verilog语言编程，试验板为DE0-Arbitrary Waveform Generator FPGA implementation, Verilog language programming, test panels of DE0
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDS_FPGA\AD_FPGA_TOP.bdf
........\db\altsyncram_0o91.tdf
........\..\altsyncram_2124.tdf
........\..\altsyncram_2r14.tdf
........\..\altsyncram_6124.tdf
........\..\altsyncram_8124.tdf
........\..\altsyncram_au14.tdf
........\..\altsyncram_b191.tdf
........\..\altsyncram_bu14.tdf
........\..\altsyncram_cr14.tdf
........\..\altsyncram_eu14.tdf
........\..\altsyncram_ir14.tdf
........\..\cmpr_ngc.tdf
........\..\cmpr_pgc.tdf
........\..\cmpr_qgc.tdf
........\..\cmpr_rgc.tdf
........\..\cmpr_sgc.tdf
........\..\cntr_05j.tdf
........\..\cntr_1fi.tdf
........\..\cntr_23j.tdf
........\..\cntr_bbj.tdf
........\..\cntr_cgi.tdf
........\..\cntr_egi.tdf
........\..\cntr_fgi.tdf
........\..\cntr_g9j.tdf
........\..\cntr_ggi.tdf
........\..\cntr_hgi.tdf
........\..\cntr_i6j.tdf
........\..\cntr_igi.tdf
........\..\cntr_jgi.tdf
........\..\cntr_kgi.tdf
........\..\cntr_o9j.tdf
........\..\cntr_tei.tdf
........\..\DDS_FPGA.ace_cmp.bpm
........\..\DDS_FPGA.ace_cmp.cdb
........\..\DDS_FPGA.ace_cmp.hdb
........\..\DDS_FPGA.amm.cdb
........\..\DDS_FPGA.asm.qmsg
........\..\DDS_FPGA.asm.rdb
........\..\DDS_FPGA.asm_labs.ddb
........\..\DDS_FPGA.cbx.xml
........\..\DDS_FPGA.cmp.bpm
........\..\DDS_FPGA.cmp.cdb
........\..\DDS_FPGA.cmp.hdb
........\..\DDS_FPGA.cmp.kpt
........\..\DDS_FPGA.cmp.logdb
........\..\DDS_FPGA.cmp.rdb
........\..\DDS_FPGA.cmp_merge.kpt
........\..\DDS_FPGA.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
........\..\DDS_FPGA.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd
........\..\DDS_FPGA.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
........\..\DDS_FPGA.db_info
........\..\DDS_FPGA.eco.cdb
........\..\DDS_FPGA.eda.qmsg
........\..\DDS_FPGA.fit.qmsg
........\..\DDS_FPGA.hier_info
........\..\DDS_FPGA.hif
........\..\DDS_FPGA.idb.cdb
........\..\DDS_FPGA.lpc.html
........\..\DDS_FPGA.lpc.rdb
........\..\DDS_FPGA.lpc.txt
........\..\DDS_FPGA.map.bpm
........\..\DDS_FPGA.map.cdb
........\..\DDS_FPGA.map.hdb
........\..\DDS_FPGA.map.kpt
........\..\DDS_FPGA.map.logdb
........\..\DDS_FPGA.map.qmsg
........\..\DDS_FPGA.map_bb.cdb
........\..\DDS_FPGA.map_bb.hdb
........\..\DDS_FPGA.map_bb.logdb
........\..\DDS_FPGA.pre_map.cdb
........\..\DDS_FPGA.pre_map.hdb
........\..\DDS_FPGA.rtlv.hdb
........\..\DDS_FPGA.rtlv_sg.cdb
........\..\DDS_FPGA.rtlv_sg_swap.cdb
........\..\DDS_FPGA.sgdiff.cdb
........\..\DDS_FPGA.sgdiff.hdb
........\..\DDS_FPGA.sld_design_entry.sci
........\..\DDS_FPGA.sld_design_entry_dsc.sci
........\..\DDS_FPGA.smart_action.txt
........\..\DDS_FPGA.sta.qmsg
........\..\DDS_FPGA.sta.rdb
........\..\DDS_FPGA.sta_cmp.6_slow_1200mv_85c.tdb
........\..\DDS_FPGA.syn_hier_info
........\..\DDS_FPGA.taw.rdb
........\..\DDS_FPGA.tiscmp.fast_1200mv_0c.ddb
........\..\DDS_FPGA.tiscmp.slow_1200mv_0c.ddb
........\..\DDS_FPGA.tiscmp.slow_1200mv_85c.ddb
........\..\DDS_FPGA.tis_db_list.ddb
........\..\dds_pll_altpll.v
........\..\decode_dvf.tdf
........\..\decode_jsa.tdf
........\..\logic_util_heursitic.dat
........\..\mux_1tc.tdf
........\..\mux_hob.tdf
........\..\mux_qsc.tdf
........\..\mux_rsc.tdf
........\..\mux_ssc.tdf
........\..\mux_vsc.tdf
........\..\PLL_altpll.v