文件名称:encoder-based-on-Gray-code
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基于VHDL格雷码编码器的设计，可以在试验箱上直接运行-Design of VHDL encoder based on Gray code, can be run directly in the chamber
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下载文件列表
基于VHDL格雷码编码器的设计\exp2.asm.rpt
..........................\exp2.done
..........................\exp2.eda.rpt
..........................\exp2.fit.eqn
..........................\exp2.fit.rpt
..........................\exp2.fit.smsg
..........................\exp2.fit.summary
..........................\exp2.flow.rpt
..........................\exp2.map.eqn
..........................\exp2.map.rpt
..........................\exp2.map.summary
..........................\exp2.pin
..........................\exp2.pof
..........................\exp2.qpf
..........................\exp2.qsf
..........................\exp2.qws
..........................\exp2.sof
..........................\exp2.sta.rpt
..........................\exp2.sta.summary
..........................\exp2.tan.rpt
..........................\exp2.tan.summary
..........................\exp2.vhd
..........................\exp2_assignment_defaults.qdf
..........................\incremental_db\compiled_partitions\exp2.root_partition.map.kpt
..........................\..............\README
..........................\simulation\modelsim\exp2.sft
..........................\..........\........\exp2.vho
..........................\..........\........\exp2_8_1200mv_0c_vhd_slow.sdo
..........................\..........\........\exp2_8_1200mv_85c_vhd_slow.sdo
..........................\..........\........\exp2_min_1200mv_0c_vhd_fast.sdo
..........................\..........\........\exp2_modelsim.xrf
..........................\..........\........\exp2_vhd.sdo
..........................\timing\primetime\exp2.vho
..........................\......\.........\exp2_pt_vhd.tcl
..........................\......\.........\exp2_vhd.sdo
..........................\incremental_db\compiled_partitions
..........................\simulation\modelsim
..........................\timing\primetime
..........................\db
..........................\incremental_db
..........................\simulation
..........................\timing
基于VHDL格雷码编码器的设计