文件名称:CLK_DIV_IP_packager
- 所属分类：
- VHDL编程
- 资源属性：
- [Linux] [SHELL] [源码]
- 上传时间：
- 2015-12-31
- 文件大小：
- 674kb
- 下载次数：
- 0次
- 提 供 者：
- LIU-Ji*******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
Vivado IP packager的实例。Vivado版本2014.2，使用Verilog语言对一个分频程序打包。-Examples of Vivado IP packager. Vivado version 2014.2, using the Verilog language for a division of the program package.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
CLK_DIV
.......\CLK_DIV.cache
.......\.............\compile_simlib
.......\CLK_DIV.data
.......\............\constrs_1
.......\............\.........\fileset.xml
.......\............\runs
.......\............\....\impl_1
.......\............\....\......\constrs_in.xml
.......\............\....\......\impl_1.psg
.......\............\....\impl_1.psg
.......\............\....\runs.xml
.......\............\....\synth_1
.......\............\....\.......\constrs_in.xml
.......\............\....\.......\sources.xml
.......\............\....\.......\synth_1.psg
.......\............\....\synth_1.psg
.......\............\sim_1
.......\............\.....\fileset.xml
.......\............\sources_1
.......\............\.........\fileset.xml
.......\............\wt
.......\............\..\java_command_handlers.wdf
.......\............\..\project.wpc
.......\............\..\synthesis.wdf
.......\............\..\webtalk_pa.xml
.......\............\..\xsim.wdf
.......\CLK_DIV.runs
.......\............\.jobs
.......\............\.....\vrs_config_1.xml
.......\............\.....\vrs_config_2.xml
.......\............\.....\vrs_config_3.xml
.......\............\impl_1
.......\............\......\.Vivado Implementation.queue.rst
.......\............\......\.Xil
.......\............\......\.init_design.begin.rst
.......\............\......\.init_design.end.rst
.......\............\......\.opt_design.begin.rst
.......\............\......\.opt_design.end.rst
.......\............\......\.place_design.begin.rst
.......\............\......\.place_design.end.rst
.......\............\......\.route_design.begin.rst
.......\............\......\.route_design.end.rst
.......\............\......\.vivado.begin.rst
.......\............\......\.vivado.end.rst
.......\............\......\CLK_DIV.rdi
.......\............\......\CLK_DIV.tcl
.......\............\......\CLK_DIV_clock_utilization_placed.rpt
.......\............\......\CLK_DIV_control_sets_placed.rpt
.......\............\......\CLK_DIV_drc_routed.pb
.......\............\......\CLK_DIV_drc_routed.rpt
.......\............\......\CLK_DIV_io_placed.rpt
.......\............\......\CLK_DIV_opt.dcp
.......\............\......\CLK_DIV_placed.dcp
.......\............\......\CLK_DIV_power_routed.rpt
.......\............\......\CLK_DIV_power_summary_routed.pb
.......\............\......\CLK_DIV_route_status.pb
.......\............\......\CLK_DIV_route_status.rpt
.......\............\......\CLK_DIV_routed.dcp
.......\............\......\CLK_DIV_timing_summary_routed.pb
.......\............\......\CLK_DIV_timing_summary_routed.rpt
.......\............\......\CLK_DIV_utilization_placed.pb
.......\............\......\CLK_DIV_utilization_placed.rpt
.......\............\......\ISEWrap.js
.......\............\......\ISEWrap.sh
.......\............\......\htr.txt
.......\............\......\init_design.pb
.......\............\......\opt_design.pb
.......\............\......\place_design.pb
.......\............\......\project.wdf
.......\............\......\route_design.pb
.......\............\......\rundef.js
.......\............\......\runme.bat
.......\............\......\runme.log
.......\............\......\runme.sh
.......\............\......\vivado.jou
.......\............\......\vivado.pb
.......\............\synth_1
.......\............\.......\.Vivado Synthesis.queue.rst
.......\............\.......\.Xil
.......\............\.......\....\CLK_DIV_propImpl.xdc
.......\............\.......\....\Vivado-10092-
.......\............\.......\....\.............\elab.rtd
.......\............\.......\....\.............\realtime
.......\............\.......\....\.............\........\CLK_DIV.tcl
.......\............\.......\....\.............\........\CLK_DIV_synth.xdc
.......\............\.......\....\.............\........\dupFiles.rpt
.......\............\.......\....\.............\wt
.......\............\.......\....\.............\..\project.wpc
.......\............\.......\.vivado.begin.rst
.......\............\.......\.vivado.end.rst
.......\............\.......\CLK_DIV.dcp
.......\............\.......\CLK_DI