文件名称:TIMER
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用Verilog语言模拟的数字时钟的功能,时分秒工能都有,适合做毕设,完整工程-Verilog language simulation of the digital clock function, the time of the second division of the work can be, for the completion of the project, complete
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下载文件列表
数字时钟\clock\clock.asm.rpt
........\.....\clock.done
........\.....\clock.fit.eqn
........\.....\clock.fit.rpt
........\.....\clock.fit.summary
........\.....\clock.flow.rpt
........\.....\clock.map.eqn
........\.....\clock.map.rpt
........\.....\clock.map.summary
........\.....\clock.pin
........\.....\clock.pof
........\.....\clock.qpf
........\.....\clock.qsf
........\.....\clock.qws
........\.....\clock.tan.rpt
........\.....\clock.tan.summary
........\.....\clock.vhd
........\.....\clock.vwf
........\.....\cmp_state.ini
........\.....\db\clock.asm.qmsg
........\.....\..\clock.cbx.xml
........\.....\..\clock.cmp.cdb
........\.....\..\clock.cmp.hdb
........\.....\..\clock.cmp.rdb
........\.....\..\clock.cmp.tdb
........\.....\..\clock.cmp0.ddb
........\.....\..\clock.db_info
........\.....\..\clock.eco.cdb
........\.....\..\clock.fit.qmsg
........\.....\..\clock.hier_info
........\.....\..\clock.hif
........\.....\..\clock.map.cdb
........\.....\..\clock.map.hdb
........\.....\..\clock.map.qmsg
........\.....\..\clock.pre_map.cdb
........\.....\..\clock.pre_map.hdb
........\.....\..\clock.psp
........\.....\..\clock.rtlv.hdb
........\.....\..\clock.rtlv_sg.cdb
........\.....\..\clock.rtlv_sg_swap.cdb
........\.....\..\clock.sgdiff.cdb
........\.....\..\clock.sgdiff.hdb
........\.....\..\clock.sld_design_entry.sci
........\.....\..\clock.sld_design_entry_dsc.sci
........\.....\..\clock.syn_hier_info
........\.....\..\clock.tan.qmsg
........\clock.asm.rpt
........\clock.bdf
........\clock.cdf
........\clock.done
........\clock.dpf
........\clock.fit.eqn
........\clock.fit.rpt
........\clock.fit.summary
........\clock.flow.rpt
........\clock.map.eqn
........\clock.map.rpt
........\clock.map.summary
........\clock.pin
........\clock.pof
........\clock.qpf
........\clock.qsf
........\clock.qws
........\clock.tan.rpt
........\clock.tan.summary
........\clock_assignment_defaults.qdf
........\cmp_state.ini
........\db\add_sub_0eh.tdf
........\..\add_sub_9ph.tdf
........\..\add_sub_aph.tdf
........\..\add_sub_bph.tdf
........\..\add_sub_vdh.tdf
........\..\clock.asm.qmsg
........\..\clock.cbx.xml
........\..\clock.cmp.cdb
........\..\clock.cmp.hdb
........\..\clock.cmp.logdb
........\..\clock.cmp.rdb
........\..\clock.cmp.tdb
........\..\clock.cmp0.ddb
........\..\clock.dbp
........\..\clock.db_info
........\..\clock.eco.cdb
........\..\clock.fit.qmsg
........\..\clock.hier_info
........\..\clock.hif
........\..\clock.map.cdb
........\..\clock.map.hdb
........\..\clock.map.logdb
........\..\clock.map.qmsg
........\..\clock.pre_map.cdb
........\..\clock.pre_map.hdb
........\..\clock.psp
........\..\clock.pss
........\..\clock.rtlv.hdb
........\..\clock.rtlv_sg.cdb
........\..\clock.rtlv_sg_swap.cdb
........\..\clock.sgdiff.cdb
........\..\clock.sgdiff.hdb
........\..\clock.sld_design_entry.sci