文件名称:yiweijicunqi
介绍说明－－下载内容均来自于网络，请自行研究使用
使用并置“&”法写出通用移位寄存器的VHDL模型。在时钟控制下将输入数据寄存，在满足输出条件时输出数据。-Use and set & method common shift register to write VHDL models. Under clock control the input data registers, the output data in the output condition is satisfied.
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下载文件列表
db
..\prev_cmp_yiwei.map.qmsg
..\prev_cmp_yiwei.qmsg
..\prev_cmp_yiwei.sim.qmsg
..\wed.wsf
..\yiwei.cbx.xml
..\yiwei.cmp.rdb
..\yiwei.cmp_merge.kpt
..\yiwei.db_info
..\yiwei.eco.cdb
..\yiwei.eds_overflow
..\yiwei.fnsim.cdb
..\yiwei.fnsim.hdb
..\yiwei.fnsim.qmsg
..\yiwei.hier_info
..\yiwei.hif
..\yiwei.lpc.html
..\yiwei.lpc.rdb
..\yiwei.lpc.txt
..\yiwei.map.bpm
..\yiwei.map.cdb
..\yiwei.map.ecobp
..\yiwei.map.hdb
..\yiwei.map.kpt
..\yiwei.map.logdb
..\yiwei.map.qmsg
..\yiwei.map_bb.cdb
..\yiwei.map_bb.hdb
..\yiwei.map_bb.logdb
..\yiwei.pre_map.cdb
..\yiwei.pre_map.hdb
..\yiwei.rtlv.hdb
..\yiwei.rtlv_sg.cdb
..\yiwei.rtlv_sg_swap.cdb
..\yiwei.sgdiff.cdb
..\yiwei.sgdiff.hdb
..\yiwei.sim.cvwf
..\yiwei.sim.hdb
..\yiwei.sim.qmsg
..\yiwei.sim.rdb
..\yiwei.simfam
..\yiwei.sld_design_entry.sci
..\yiwei.sld_design_entry_dsc.sci
..\yiwei.syn_hier_info
..\yiwei.tis_db_list.ddb
incremental_db
..............\compiled_partitions
..............\...................\yiwei.root_partition.map.atm
..............\...................\yiwei.root_partition.map.dpi
..............\...................\yiwei.root_partition.map.hdbx
..............\...................\yiwei.root_partition.map.kpt
..............\README
shft.vhd
shft.vhd.bak
yiwei.done
yiwei.flow.rpt
yiwei.map.rpt
yiwei.map.summary
yiwei.qpf
yiwei.qsf
yiwei.qws
yiwei.sim.rpt
yiwei.vwf
移位.jpg
移位2.jpg