文件名称:Pulse-Generator-Final-Zip
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A VHDL pulse generator that generates customizable square wave pulses on an arbitrary number of channels. Controlled by UART communication through serial port. Tuned for 5ns period clock signal.
The pulse width and delay of each channel is fully adjustable through serial port while the design is running. Channels can also be turned on and off.
The pulse width and delay of each channel is fully adjustable through serial port while the design is running. Channels can also be turned on and off.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Pulse Generator Final Zip\channel_generator.v14.vhd
.........................\delay_incrementor.v12.vhd
.........................\enable.vhd
.........................\external_trigger.v10.vhd
.........................\fifo.v11.vhd
.........................\final_trigger.v12.vhd
.........................\mod_m_counter.vhd
.........................\PulseGenerator.v10.xise
.........................\trigger.v13.vhd
.........................\uart.vhd
.........................\uart_rx.vhd
.........................\uart_tx.vhd