文件名称:verilog-a-lrm-1-0
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The information contained in this draft manual represents the definition of the Verilog-A hardware descr iption
language as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warranties
whatsoever with respect to the completeness, accuracy, or applicability of the information in this draft manual
to a user’s requirements. This language is not yet fully defined and is subject to change. It is suitable for
learning how to do analog modeling and as a vehicle for providing feedback to the standards committee. Verilog-
A should not be used for production design and development.
language as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warranties
whatsoever with respect to the completeness, accuracy, or applicability of the information in this draft manual
to a user’s requirements. This language is not yet fully defined and is subject to change. It is suitable for
learning how to do analog modeling and as a vehicle for providing feedback to the standards committee. Verilog-
A should not be used for production design and development.
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verilog-a-lrm-1-0.pdf