文件名称:m_xulie
介绍说明－－下载内容均来自于网络，请自行研究使用
这是用verilogHDL写的m序列发生器，简单易用，代码非常易读-It is written verilogHDL m sequence generator, easy to use, the code is very easy to read
(系统自动生成,下载前可以参看下载内容)
下载文件列表
m_xulie\db\logic_util_heursitic.dat
.......\..\m_sequence.amm.cdb
.......\..\m_sequence.asm.qmsg
.......\..\m_sequence.asm.rdb
.......\..\m_sequence.asm_labs.ddb
.......\..\m_sequence.cbx.xml
.......\..\m_sequence.cmp.bpm
.......\..\m_sequence.cmp.cdb
.......\..\m_sequence.cmp.hdb
.......\..\m_sequence.cmp.kpt
.......\..\m_sequence.cmp.logdb
.......\..\m_sequence.cmp.rdb
.......\..\m_sequence.cmp0.ddb
.......\..\m_sequence.cmp1.ddb
.......\..\m_sequence.cmp_merge.kpt
.......\..\m_sequence.db_info
.......\..\m_sequence.eda.qmsg
.......\..\m_sequence.fit.qmsg
.......\..\m_sequence.hier_info
.......\..\m_sequence.hif
.......\..\m_sequence.idb.cdb
.......\..\m_sequence.lpc.html
.......\..\m_sequence.lpc.rdb
.......\..\m_sequence.lpc.txt
.......\..\m_sequence.map.bpm
.......\..\m_sequence.map.cdb
.......\..\m_sequence.map.hdb
.......\..\m_sequence.map.kpt
.......\..\m_sequence.map.logdb
.......\..\m_sequence.map.qmsg
.......\..\m_sequence.map_bb.cdb
.......\..\m_sequence.map_bb.hdb
.......\..\m_sequence.map_bb.logdb
.......\..\m_sequence.pre_map.cdb
.......\..\m_sequence.pre_map.hdb
.......\..\m_sequence.rtlv.hdb
.......\..\m_sequence.rtlv_sg.cdb
.......\..\m_sequence.rtlv_sg_swap.cdb
.......\..\m_sequence.sgdiff.cdb
.......\..\m_sequence.sgdiff.hdb
.......\..\m_sequence.sld_design_entry.sci
.......\..\m_sequence.sld_design_entry_dsc.sci
.......\..\m_sequence.smart_action.txt
.......\..\m_sequence.sta.qmsg
.......\..\m_sequence.sta.rdb
.......\..\m_sequence.sta_cmp.6_slow.tdb
.......\..\m_sequence.syn_hier_info
.......\..\m_sequence.tis_db_list.ddb
.......\..\m_sequence.tmw_info
.......\..\prev_cmp_m_sequence.qmsg
.......\incremental_db\compiled_partitions\m_sequence.db_info
.......\..............\...................\m_sequence.root_partition.cmp.cdb
.......\..............\...................\m_sequence.root_partition.cmp.dfp
.......\..............\...................\m_sequence.root_partition.cmp.hdb
.......\..............\...................\m_sequence.root_partition.cmp.kpt
.......\..............\...................\m_sequence.root_partition.cmp.logdb
.......\..............\...................\m_sequence.root_partition.cmp.rcfdb
.......\..............\...................\m_sequence.root_partition.map.cdb
.......\..............\...................\m_sequence.root_partition.map.dpi
.......\..............\...................\m_sequence.root_partition.map.hbdb.cdb
.......\..............\...................\m_sequence.root_partition.map.hbdb.hb_info
.......\..............\...................\m_sequence.root_partition.map.hbdb.hdb
.......\..............\...................\m_sequence.root_partition.map.hbdb.sig
.......\..............\...................\m_sequence.root_partition.map.hdb
.......\..............\...................\m_sequence.root_partition.map.kpt
.......\..............\README
.......\m_sequence.asm.rpt
.......\m_sequence.done
.......\m_sequence.eda.rpt
.......\m_sequence.fit.rpt
.......\m_sequence.fit.smsg
.......\m_sequence.fit.summary
.......\m_sequence.flow.rpt
.......\m_sequence.map.rpt
.......\m_sequence.map.summary
.......\m_sequence.pin
.......\m_sequence.pof
.......\m_sequence.qpf
.......\m_sequence.qsf
.......\m_sequence.sof
.......\m_sequence.sta.rpt
.......\m_sequence.sta.summary
.......\m_sequence.v
.......\m_sequence.v.bak
.......\m_sequence.vhd
.......\m_sequence.vhd.bak
.......\m_sequence_nativelink_simulation.rpt
.......\simulation\modelsim\msim_transcript
.......\..........\........\m_sequence.sft
.......\..........\........\m_sequence.vo
.......\..........\........\m_sequence.vt
.......\..........\........\m_sequence.vt.bak
.......\..........\........\m_sequence_fast.vo
.......\..........\........\m_sequence_modelsim.xrf
.......\..........\........\m_sequence_run_msim_rtl_verilog.do
.......\..........\........\m_sequence_run_msim_rtl_verilog.do.bak
.......\..........\........\m_sequence_run_msim_rtl_verilog.do.bak1
.......\..........\........\m_sequence_run_msim_rtl_verilog.do.bak2
.......\..........\........\m_sequence_v.sdo
.......\..........\........\m_sequence_v_fast.sdo