文件名称:_clock
介绍说明--下载内容均来自于网络,请自行研究使用
时钟,利用FPGA上的八段led数码管进行时钟计时-Clock,using eight led digital tube on the FPGA to timing
(系统自动生成,下载前可以参看下载内容)
下载文件列表
_clock\db\prev_cmp_zyh4650_clock.asm.qmsg
......\..\prev_cmp_zyh4650_clock.fit.qmsg
......\..\prev_cmp_zyh4650_clock.map.qmsg
......\..\prev_cmp_zyh4650_clock.qmsg
......\..\prev_cmp_zyh4650_clock.sim.qmsg
......\..\prev_cmp_zyh4650_clock.sta.qmsg
......\..\wed.wsf
......\..\zyh4650_clock.asm.qmsg
......\..\zyh4650_clock.cbx.xml
......\..\zyh4650_clock.cmp.bpm
......\..\zyh4650_clock.cmp.cdb
......\..\zyh4650_clock.cmp.ecobp
......\..\zyh4650_clock.cmp.hdb
......\..\zyh4650_clock.cmp.kpt
......\..\zyh4650_clock.cmp.logdb
......\..\zyh4650_clock.cmp.rdb
......\..\zyh4650_clock.cmp_merge.kpt
......\..\zyh4650_clock.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
......\..\zyh4650_clock.cuda_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
......\..\zyh4650_clock.db_info
......\..\zyh4650_clock.eco.cdb
......\..\zyh4650_clock.eds_overflow
......\..\zyh4650_clock.fit.qmsg
......\..\zyh4650_clock.fnsim.cdb
......\..\zyh4650_clock.fnsim.hdb
......\..\zyh4650_clock.fnsim.qmsg
......\..\zyh4650_clock.hier_info
......\..\zyh4650_clock.hif
......\..\zyh4650_clock.lpc.html
......\..\zyh4650_clock.lpc.rdb
......\..\zyh4650_clock.lpc.txt
......\..\zyh4650_clock.map.bpm
......\..\zyh4650_clock.map.cdb
......\..\zyh4650_clock.map.ecobp
......\..\zyh4650_clock.map.hdb
......\..\zyh4650_clock.map.kpt
......\..\zyh4650_clock.map.logdb
......\..\zyh4650_clock.map.qmsg
......\..\zyh4650_clock.map_bb.cdb
......\..\zyh4650_clock.map_bb.hdb
......\..\zyh4650_clock.map_bb.logdb
......\..\zyh4650_clock.pre_map.cdb
......\..\zyh4650_clock.pre_map.hdb
......\..\zyh4650_clock.rtlv.hdb
......\..\zyh4650_clock.rtlv_sg.cdb
......\..\zyh4650_clock.rtlv_sg_swap.cdb
......\..\zyh4650_clock.sgdiff.cdb
......\..\zyh4650_clock.sgdiff.hdb
......\..\zyh4650_clock.sim.cvwf
......\..\zyh4650_clock.sim.hdb
......\..\zyh4650_clock.sim.qmsg
......\..\zyh4650_clock.sim.rdb
......\..\zyh4650_clock.simfam
......\..\zyh4650_clock.sld_design_entry.sci
......\..\zyh4650_clock.sld_design_entry_dsc.sci
......\..\zyh4650_clock.sta.qmsg
......\..\zyh4650_clock.sta.rdb
......\..\zyh4650_clock.sta_cmp.7_slow_1200mv_85c.tdb
......\..\zyh4650_clock.syn_hier_info
......\..\zyh4650_clock.tiscmp.fast_1200mv_0c.ddb
......\..\zyh4650_clock.tiscmp.slow_1200mv_0c.ddb
......\..\zyh4650_clock.tiscmp.slow_1200mv_85c.ddb
......\..\zyh4650_clock.tis_db_list.ddb
......\..\zyh4650_clock_global_asgn_op.abo
......\incremental_db\compiled_partitions\zyh4650_clock.root_partition.cmp.atm
......\..............\...................\zyh4650_clock.root_partition.cmp.dfp
......\..............\...................\zyh4650_clock.root_partition.cmp.hdbx
......\..............\...................\zyh4650_clock.root_partition.cmp.kpt
......\..............\...................\zyh4650_clock.root_partition.cmp.logdb
......\..............\...................\zyh4650_clock.root_partition.cmp.rcf
......\..............\...................\zyh4650_clock.root_partition.map.atm
......\..............\...................\zyh4650_clock.root_partition.map.dpi
......\..............\...................\zyh4650_clock.root_partition.map.hdbx
......\..............\...................\zyh4650_clock.root_partition.map.kpt
......\..............\README
......\serv_req_info.txt
......\zyh4650_baoshi.bsf
......\zyh4650_baoshi.vhd
......\zyh4650_baoshi.vhd.bak
......\zyh4650_baoshi.vwf
......\zyh4650_clock.asm.rpt
......\zyh4650_clock.bdf
......\zyh4650_clock.cdf
......\zyh4650_clock.done
......\zyh4650_clock.dpf
......\zyh4650_clock.fit.rpt
......\zyh4650_clock.fit.smsg
......\zyh4650_clock.fit.summary
......\zyh4650_clock.flow.rpt
......\zyh4650_clock.map.rpt
......\zyh4650_clock.map.summary
......\zyh4650_clock.pin
......\zyh4650_clock.qpf
......\zyh4650_clock.qsf
......\zyh4650_clock.qws
......\zyh4650_clock.sim.rpt
......\zyh4650_clock.sof
......\zyh4650_clock.sta.rpt
......\zyh4650_clock.sta.summary
......\zyh4650_cnt12_24.bsf