文件名称:Project6(finish)
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modelsim下仿真通过，用Verilog写的多周期CPU，是计算机组成原理的大作业，供学弟学妹参考。-Under modelsim simulation by using Verilog write multi-cycle CPU, is composed of a large computer operating principle for mentees reference.
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下载文件列表
Project6(finish)\alu.v
................\be_load.v
................\be_save.v
................\code.txt
................\controller.v
................\controller.v.bak
................\dm.v
................\ext.v
................\gpr.v
................\head_mips.v
................\im.v
................\mips.cr.mti
................\mips.mpf
................\mips.v
................\mux.v
................\npc.v
................\pc.v
................\testbench.v
................\vsim.wlf
................\wave1.bmp
................\wave2.bmp
................\.ork\alu\verilog.asm64
................\....\...\verilog.rw64
................\....\...\_primary.dat
................\....\...\_primary.dbs
................\....\...\_primary.vhd
................\....\be_load\verilog.asm64
................\....\.......\verilog.rw64
................\....\.......\_primary.dat
................\....\.......\_primary.dbs
................\....\.......\_primary.vhd
................\....\...save\verilog.asm64
................\....\.......\verilog.rw64
................\....\.......\_primary.dat
................\....\.......\_primary.dbs
................\....\.......\_primary.vhd
................\....\controller\verilog.asm64
................\....\..........\verilog.rw64
................\....\..........\_primary.dat
................\....\..........\_primary.dbs
................\....\..........\_primary.vhd
................\....\dm\verilog.asm64
................\....\..\verilog.rw64
................\....\..\_primary.dat
................\....\..\_primary.dbs
................\....\..\_primary.vhd
................\....\gpr\verilog.asm64
................\....\...\verilog.rw64
................\....\...\_primary.dat
................\....\...\_primary.dbs
................\....\...\_primary.vhd
................\....\im\verilog.asm64
................\....\..\verilog.rw64
................\....\..\_primary.dat
................\....\..\_primary.dbs
................\....\..\_primary.vhd
................\....\mips\verilog.asm64
................\....\....\verilog.rw64
................\....\....\_primary.dat
................\....\....\_primary.dbs
................\....\....\_primary.vhd
................\....\.ux32\verilog.asm64
................\....\.....\verilog.rw64
................\....\.....\_primary.dat
................\....\.....\_primary.dbs
................\....\.....\_primary.vhd
................\....\...5\verilog.asm64
................\....\....\verilog.rw64
................\....\....\_primary.dat
................\....\....\_primary.dbs
................\....\....\_primary.vhd
................\....\npc\verilog.asm64
................\....\...\verilog.rw64
................\....\...\_primary.dat
................\....\...\_primary.dbs
................\....\...\_primary.vhd
................\....\pc\verilog.asm64
................\....\..\verilog.rw64
................\....\..\_primary.dat
................\....\..\_primary.dbs
................\....\..\_primary.vhd
................\....\sign_ext\verilog.asm64
................\....\........\verilog.rw64
................\....\........\_primary.dat
................\....\........\_primary.dbs
................\....\........\_primary.vhd
................\....\testbench_mips\verilog.asm64
................\....\..............\verilog.rw64
................\....\..............\_primary.dat
................\....\..............\_primary.dbs
................\....\..............\_primary.vhd
................\....\zero_ext\verilog.asm64
................\....\........\verilog.rw64
................\....\........\_primary.dat
................\....\........\_primary.dbs
................\....\........\_primary.vhd
................\....\_info
................\....\_vmake
................\....\alu
................\....\be_load