文件名称:Example-b8-1
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
使用ModelSim对Altera设计进行功能仿真的简要操作步骤 1.建立仿真工程
2.Altera仿真库的编译与映射
3.编译HDL源代码和Testbench
4.启动仿真器并加载设计顶层
5.打开观测窗口，添加信号
6.执行仿真-Using ModelSim Altera design for functional simulation brief Procedure 1. Create a simulation project
Compilation and mapping 2.Altera emulation library
3. Compile HDL source code and Testbench
4. Start the emulator and the top load design
5. Open the observation window, add signals
6. execution simulation
2.Altera仿真库的编译与映射
3.编译HDL源代码和Testbench
4.启动仿真器并加载设计顶层
5.打开观测窗口，添加信号
6.执行仿真-Using ModelSim Altera design for functional simulation brief Procedure 1. Create a simulation project
Compilation and mapping 2.Altera emulation library
3. Compile HDL source code and Testbench
4. Start the emulator and the top load design
5. Open the observation window, add signals
6. execution simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Example-b8-1\Altera_lib_files\220model.txt
............\................\220model.v
............\................\220model.vhd
............\................\220model_87.vhd
............\................\220pack.vhd
............\................\altera_mf.txt
............\................\altera_mf.v
............\................\altera_mf.vhd
............\................\altera_mf_87.vhd
............\................\altera_mf_components.vhd
............\................\stratix_atoms.v
............\................\stratix_atoms.vhd
............\................\stratix_components.vhd
............\func_sim\dpram8x32.v
............\........\func_sim.cr.mti
............\........\func_sim.mpf
............\........\func_sim_wave.wlf
............\........\pllx2.v
............\........\pll_ram.v
............\........\pll_ram_tb.v
............\........\transcript
............\........\vsim.wlf
............\........\wave.bmp
............\........\wave.do
............\........\.ork\dpram8x32\verilog.asm
............\........\....\.........\_primary.dat
............\........\....\.........\_primary.vhd
............\........\....\pllx2\verilog.asm
............\........\....\.....\_primary.dat
............\........\....\.....\_primary.vhd
............\........\....\..._ram\verilog.asm
............\........\....\.......\_primary.dat
............\........\....\.......\_primary.vhd
............\........\....\......._tb\verilog.asm
............\........\....\..........\_primary.dat
............\........\....\..........\_primary.vhd
............\........\....\_info
............\pll_ram\cmp_state.ini
............\.......\db\altsyncram_06q1.tdf
............\.......\..\altsyncram_7bc1.tdf
............\.......\..\altsyncram_bvp1.tdf
............\.......\..\pll_ram.asm.qmsg
............\.......\..\pll_ram.asm_labs.ddb
............\.......\..\pll_ram.cbx.xml
............\.......\..\pll_ram.cmp.cdb
............\.......\..\pll_ram.cmp.hdb
............\.......\..\pll_ram.cmp.logdb
............\.......\..\pll_ram.cmp.rdb
............\.......\..\pll_ram.cmp.tdb
............\.......\..\pll_ram.cmp0.ddb
............\.......\..\pll_ram.cmp2.ddb
............\.......\..\pll_ram.dbp
............\.......\..\pll_ram.db_info
............\.......\..\pll_ram.eco.cdb
............\.......\..\pll_ram.eda.qmsg
............\.......\..\pll_ram.fit.qmsg
............\.......\..\pll_ram.hier_info
............\.......\..\pll_ram.hif
............\.......\..\pll_ram.map.cdb
............\.......\..\pll_ram.map.hdb
............\.......\..\pll_ram.map.logdb
............\.......\..\pll_ram.map.qmsg
............\.......\..\pll_ram.pre_map.cdb
............\.......\..\pll_ram.pre_map.hdb
............\.......\..\pll_ram.psp
............\.......\..\pll_ram.pss
............\.......\..\pll_ram.rpp.qmsg
............\.......\..\pll_ram.rtlv.hdb
............\.......\..\pll_ram.rtlv_sg.cdb
............\.......\..\pll_ram.rtlv_sg_swap.cdb
............\.......\..\pll_ram.sgate.rvd
............\.......\..\pll_ram.sgate_sm.rvd
............\.......\..\pll_ram.sgdiff.cdb
............\.......\..\pll_ram.sgdiff.hdb
............\.......\..\pll_ram.signalprobe.cdb
............\.......\..\pll_ram.sld_design_entry.sci
............\.......\..\pll_ram.sld_design_entry_dsc.sci
............\.......\..\pll_ram.syn_hier_info
............\.......\..\pll_ram.tan.qmsg
............\.......\..\pll_ram.tis_db_list.ddb
............\.......\..\pll_ram_cmp.qrpt
............\.......\..\pll_ram_hier_info
............\.......\..\pll_ram_syn_hier_info
............\.......\..\prev_cmp_pll_ram.asm.qmsg
............\.......\..\prev_cmp_pll_ram.eda.qmsg
............\.......\..\prev_cmp_pll_ram.fit.qmsg
............\.......\..\prev_cmp_pll_ram.map.qmsg
............\.......\..\prev_cmp_pll_ram.qmsg
............\.......\..\prev_cmp_pll_ram.tan.qmsg
............\.......\dpram8x32.v
............\.......\pllx2.v
............\.......\pll_ram.asm.rpt
............\.......\pll_ram.done
............\.......\pll_ram.eda.rpt
............\.......\pll_ram.fit.eqn
............\.......\pll_ram.fit.rpt
............\.......\pll_ram.