文件名称:6modified_booth_multiplier_module
- 所属分类：
- 其他小程序
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2014-12-17
- 文件大小：
- 520kb
- 下载次数：
- 0次
- 提 供 者：
- cheng*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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利用Verilog编写的ModifiedBooth乘法器，对想学习乘法器的将会有很大的帮助-Use Verilog prepared ModifiedBooth multiplier, multiplier will want to learn a great help
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下载文件列表
Experiment06\db\logic_util_heursitic.dat
............\..\modified_booth_multiplier_module.db_info
............\..\prev_cmp_modified_booth_multiplier_module.qmsg
............\incremental_db\compiled_partitions\modified_booth_multiplier_module.db_info
............\..............\...................\modified_booth_multiplier_module.root_partition.cmp.dfp
............\..............\...................\modified_booth_multiplier_module.root_partition.cmp.kpt
............\..............\...................\modified_booth_multiplier_module.root_partition.cmp.logdb
............\..............\...................\modified_booth_multiplier_module.root_partition.map.dpi
............\..............\...................\modified_booth_multiplier_module.root_partition.map.kpt
............\..............\README
............\modified_booth_multiplier_module.asm.rpt
............\modified_booth_multiplier_module.done
............\modified_booth_multiplier_module.eda.rpt
............\modified_booth_multiplier_module.fit.rpt
............\modified_booth_multiplier_module.fit.summary
............\modified_booth_multiplier_module.flow.rpt
............\modified_booth_multiplier_module.map.rpt
............\modified_booth_multiplier_module.map.smsg
............\modified_booth_multiplier_module.map.summary
............\modified_booth_multiplier_module.pin
............\modified_booth_multiplier_module.pof
............\modified_booth_multiplier_module.qpf
............\modified_booth_multiplier_module.qsf
............\modified_booth_multiplier_module.sof
............\modified_booth_multiplier_module.tan.rpt
............\modified_booth_multiplier_module.tan.summary
............\modified_booth_multiplier_module.v
............\modified_booth_multiplier_module.v.bak
............\modified_booth_multiplier_module_assignment_defaults.qdf
............\modified_booth_multiplier_module_nativelink_simulation.rpt
............\simulation\modelsim\modelsim.ini
............\..........\........\modified_booth_multiplier_module.sft
............\..........\........\modified_booth_multiplier_module.vo
............\..........\........\modified_booth_multiplier_module.vt
............\..........\........\modified_booth_multiplier_module.vt.bak
............\..........\........\modified_booth_multiplier_module_modelsim.xrf
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak1
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak2
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak3
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak4
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak5
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak6
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak7
............\..........\........\modified_booth_multiplier_module_run_msim_rtl_verilog.do.bak8
............\..........\........\modified_booth_multiplier_module_v.sdo
............\..........\........\msim_transcript
............\..........\........\rtl_work\modified_booth_multiplier_module\verilog.prw
............\..........\........\........\................................\verilog.psm
............\..........\........\........\................................\_primary.dat
............\..........\........\........\................................\_primary.dbs
............\..........\........\........\................................\_primary.vhd
............\..........\........\........\................................_simulation\verilog.prw
............\..........\........\........\...........................................\verilog.psm
............\..........\........\........\.........................................