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FPGA 实现全双工异步串口（UART），与PC 机通信。1 位起始位；8 位数据位；一个停止位；无校验位；波特率为2400、4800、9600、11520 任选或可变（可用按键控制波特率模式）-FPGA to achieve full-duplex asynchronous serial interface (UART), to communicate with the PC. A start bit 8 data bits one stop bit no parity bit 2400,4800,9600,11520 optional or variable baud rate (baud rate mode button control available)
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下载文件列表
vhdl\example\Chapter5 Sample\UART
....\.......\...............\....\automake.log
....\.......\...............\....\baudrate_generator.jhd
....\.......\...............\....\baudrate_generator.vhd
....\.......\...............\....\baudrate_generator_TB.jhd
....\.......\...............\....\baudrate_generator_TB.vhd
....\.......\...............\....\counter.jhd
....\.......\...............\....\counter.vhd
....\.......\...............\....\counter_TB.jhd
....\.......\...............\....\counter_TB.vhd
....\.......\...............\....\detector.jhd
....\.......\...............\....\detector.vhd
....\.......\...............\....\detector_TB.jhd
....\.......\...............\....\detector_TB.vhd
....\.......\...............\....\parity_verifier.jhd
....\.......\...............\....\parity_verifier.vhd
....\.......\...............\....\parity_verifier_TB.jhd
....\.......\...............\....\parity_verifier_TB.vhd
....\.......\...............\....\shift_register.jhd
....\.......\...............\....\shift_register.vhd
....\.......\...............\....\shift_register_TB.jhd
....\.......\...............\....\shift_register_TB.vhd
....\.......\...............\....\switch.jhd
....\.......\...............\....\switch.vhd
....\.......\...............\....\switch_bus.jhd
....\.......\...............\....\switch_bus.vhd
....\.......\...............\....\switch_bus_TB.jhd
....\.......\...............\....\switch_bus_TB.vhd
....\.......\...............\....\UART.npl
....\.......\...............\....\uart_core.jhd
....\.......\...............\....\uart_core.vhd
....\.......\...............\....\UART_PACKAGE.vhd
....\.......\...............\....\uart_top.jhd
....\.......\...............\....\uart_top.vhd
....\.......\...............\....\uart_top_tb.jhd
....\.......\...............\....\uart_top_tb.vhd
....\.......\...............\....\__projnav
....\.......\...............\....\__projnav.log
....\.......\...............\....\.........\p00p5000.kis
....\.......\...............\....\.........\p00pi000.kis
....\.......\...............\....\.........\p00pl000.kis
....\.......\...............\....\.........\runXst_tcl.rsp