文件名称:sha1_v01
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sha1_testbench.v
-- Testbench with vectors NIST FIPS 180-2
sha1_exec.v
-- Top level sha1 module
sha1_round.v
-- primitive sha1 round
dffhr.v
-- generic parameterizable D-flip flop library
Performance Analysis
Performance equation of core is
frequency in MHz * (512bits/block) / (81 rounds/block). The
cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7
FPGA which results in 700 Mbps processing rate.
Note: This calculation ignores the effect of a partially full
last block
Finally, Padding, HMAC, and bus interface functionality is not
provided. These will vary with the particular system design.
The core size is about 800 Xilinx Virtex II FPGA Family Slices.
I welcome feedback on any aspects of this design.-sha1_testbench.v
-- Testbench with vectors NIST FIPS 180-2
sha1_exec.v
-- Top level sha1 module
sha1_round.v
-- primitive sha1 round
dffhr.v
-- generic parameterizable D-flip flop library
Performance Analysis
Performance equation of core is
frequency in MHz * (512bits/block) / (81 rounds/block). The
cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7
FPGA which results in 700 Mbps processing rate.
Note: This calculation ignores the effect of a partially full
last block
Finally, Padding, HMAC, and bus interface functionality is not
provided. These will vary with the particular system design.
The core size is about 800 Xilinx Virtex II FPGA Family Slices.
I welcome feedback on any aspects of this design.
-- Testbench with vectors NIST FIPS 180-2
sha1_exec.v
-- Top level sha1 module
sha1_round.v
-- primitive sha1 round
dffhr.v
-- generic parameterizable D-flip flop library
Performance Analysis
Performance equation of core is
frequency in MHz * (512bits/block) / (81 rounds/block). The
cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7
FPGA which results in 700 Mbps processing rate.
Note: This calculation ignores the effect of a partially full
last block
Finally, Padding, HMAC, and bus interface functionality is not
provided. These will vary with the particular system design.
The core size is about 800 Xilinx Virtex II FPGA Family Slices.
I welcome feedback on any aspects of this design.-sha1_testbench.v
-- Testbench with vectors NIST FIPS 180-2
sha1_exec.v
-- Top level sha1 module
sha1_round.v
-- primitive sha1 round
dffhr.v
-- generic parameterizable D-flip flop library
Performance Analysis
Performance equation of core is
frequency in MHz * (512bits/block) / (81 rounds/block). The
cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7
FPGA which results in 700 Mbps processing rate.
Note: This calculation ignores the effect of a partially full
last block
Finally, Padding, HMAC, and bus interface functionality is not
provided. These will vary with the particular system design.
The core size is about 800 Xilinx Virtex II FPGA Family Slices.
I welcome feedback on any aspects of this design.
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下载文件列表
sha1_readme_v01.txt
sha1_round.v
sha1_testbench.v
dffhr.v
sha1_exec.v