文件名称:RCA_CLA
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comparison between ripple carry adder and carry look ahead Adder.
the saif files for dynamic power are included.
the saif files for dynamic power are included.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
CR-8bity\activity\CLA.saif
........\........\RCA.saif
........\........\sum_activity1.m
........\CLA\CLA.saif
........\...\CLA.v
........\...\CLA.vcd
........\...\modelsim\CLA.cr.mti
........\...\........\CLA.mpf
........\...\........\CLA.v
........\...\........\CLA.vcd
........\...\........\Test.v
........\...\........\transcript
........\...\........\vsim.wlf
........\...\........\work\@c@l@a\verilog.asm
........\...\........\....\......\verilog.rw
........\...\........\....\......\_primary.dat
........\...\........\....\......\_primary.dbs
........\...\........\....\......\_primary.vhd
........\...\........\....\top\verilog.asm
........\...\........\....\...\verilog.rw
........\...\........\....\...\_primary.dat
........\...\........\....\...\_primary.dbs
........\...\........\....\...\_primary.vhd
........\...\........\....\_info
........\...\........\....\_vmake
........\...\reports\C_R_delays.spef
........\...\.......\netlist.v
........\...\.......\netlist.vhd
........\...\.......\sdc.sdc
........\...\.......\Stndrd_Dly_Frmt.sdf
........\...\.......\time_report_max
........\...\.......\time_report_min
........\...\.......\timing_report
........\RCA\FA.v
........\...\modelsim\FA.v
........\...\........\RCA.cr.mti
........\...\........\RCA.mpf
........\...\........\RCA.v
........\...\........\RCA.vcd
........\...\........\TEST.v
........\...\........\vsim.wlf
........\...\........\work\@f@a\verilog.asm
........\...\........\....\....\verilog.rw
........\...\........\....\....\_primary.dat
........\...\........\....\....\_primary.dbs
........\...\........\....\....\_primary.vhd
........\...\........\....\.r@c@a\verilog.asm
........\...\........\....\......\verilog.rw
........\...\........\....\......\_primary.dat
........\...\........\....\......\_primary.dbs
........\...\........\....\......\_primary.vhd
........\...\........\....\top\verilog.asm
........\...\........\....\...\verilog.rw
........\...\........\....\...\_primary.dat
........\...\........\....\...\_primary.dbs
........\...\........\....\...\_primary.vhd
........\...\........\....\_info
........\...\........\....\_vmake
........\...\RCA.saif
........\...\RCA.v
........\...\RCA.vcd
........\...\reports\C_R_delays.spef
........\...\.......\netlist.v
........\...\.......\netlist.vhd
........\...\.......\sdc.sdc
........\...\.......\Stndrd_Dly_Frmt.sdf
........\...\.......\time_report_max
........\...\.......\time_report_min
...4bity\activity\CLA.saif
........\........\RCA.saif
........\........\sum_activity.m
........\CLA\CLA.saif
........\...\CLA.v
........\...\CLA.vcd
........\...\modelsim\CLA.cr.mti
........\...\........\CLA.mpf
........\...\........\CLA.v
........\...\........\CLA.vcd
........\...\........\Test.v
........\...\........\Test.v.bak
........\...\........\vsim.wlf
........\...\........\work\@c@l@a\verilog.asm
........\...\........\....\......\verilog.rw
........\...\........\....\......\_primary.dat
........\...\........\....\......\_primary.dbs
........\...\........\....\......\_primary.vhd
........\...\........\....\top\verilog.asm
........\...\........\....\...\verilog.rw
........\...\........\....\...\_primary.dat
........\...\........\....\...\_primary.dbs
........\...\........\....\...\_primary.vhd
........\...\........\....\_info
........\...\........\....\_vmake
........\...\reports\C_R_delays.spef
........\...\.......\netlist.v
........\...\.......\netlist.vhd
........\...\.......\sdc.sdc
........\...\.......\Stndrd_Dly_Frmt.sdf
........\...\.......\time_report_max
........\...\.......\time_report_min