文件名称:dianzizhong
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使用Verilog语言编写的电子钟，课堂小实验，经过测试可用。-Electronic clock, with Verilog language classroom experiments, after testing is available.
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下载文件列表
dianzizhong
...........\Seg_Dis.v
...........\db
...........\..\electonic_clock.db_info
...........\..\electonic_clock.sld_design_entry.sci
...........\electonic_clock.qpf
...........\electonic_clock.qsf
...........\electronic_clock.v
...........\electronic_clock.v.bak
...........\get_key.v
...........\get_key.v.bak
...........\key.v
...........\key_5.V
...........\key_5.v.bak
...........\led_display.v
...........\led_display.v.bak
...........\seg.v
...........\speaker.v
...........\speaker.v.bak
...........\timer.v
...........\timer.v.bak