文件名称:FPGA_verilog_VGA_SimpleDemo
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FPGA初级程序,基于verilog的VGA简单接口驱动-VGA-based verilog simple interface driver
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下载文件列表
基于verilog的VGA简单接口驱动\VGA显示原理与VGA时序实现.doc
............................\使用 FPGA 控制 VGA 显示.doc
............................\使用 FPGA 控制 VGA 显示.pdf
............................\基于DSP Builder的VGA接口设计.doc
............................\基于FPGA的VGA时序彩条信号实现方法及其应用.doc
............................\....verilog的VGA简单接口驱动\db\logic_util_heursitic.dat
............................\............................\..\prev_cmp_vga_dis.asm.qmsg
............................\............................\..\prev_cmp_vga_dis.fit.qmsg
............................\............................\..\prev_cmp_vga_dis.map.qmsg
............................\............................\..\prev_cmp_vga_dis.tan.qmsg
............................\............................\..\vga_dis.asm.qmsg
............................\............................\..\vga_dis.asm.rdb
............................\............................\..\vga_dis.asm_labs.ddb
............................\............................\..\vga_dis.cbx.xml
............................\............................\..\vga_dis.cmp.cdb
............................\............................\..\vga_dis.cmp.hdb
............................\............................\..\vga_dis.cmp.kpt
............................\............................\..\vga_dis.cmp.logdb
............................\............................\..\vga_dis.cmp.rdb
............................\............................\..\vga_dis.cmp.tdb
............................\............................\..\vga_dis.cmp0.ddb
............................\............................\..\vga_dis.cmp2.ddb
............................\............................\..\vga_dis.db_info
............................\............................\..\vga_dis.eco.cdb
............................\............................\..\vga_dis.fit.qmsg
............................\............................\..\vga_dis.hier_info
............................\............................\..\vga_dis.hif
............................\............................\..\vga_dis.lpc.html
............................\............................\..\vga_dis.lpc.rdb
............................\............................\..\vga_dis.lpc.txt
............................\............................\..\vga_dis.map.cdb
............................\............................\..\vga_dis.map.hdb
............................\............................\..\vga_dis.map.logdb
............................\............................\..\vga_dis.map.qmsg
............................\............................\..\vga_dis.pre_map.cdb
............................\............................\..\vga_dis.pre_map.hdb
............................\............................\..\vga_dis.rtlv.hdb
............................\............................\..\vga_dis.rtlv_sg.cdb
............................\............................\..\vga_dis.rtlv_sg_swap.cdb
............................\............................\..\vga_dis.sgdiff.cdb
............................\............................\..\vga_dis.sgdiff.hdb
............................\............................\..\vga_dis.sld_design_entry.sci
............................\............................\..\vga_dis.sld_design_entry_dsc.sci
............................\............................\..\vga_dis.smart_action.txt
............................\............................\..\vga_dis.syn_hier_info
............................\............................\..\vga_dis.tan.qmsg
............................\............................\..\vga_dis.tis_db_list.ddb
............................\............................\..\vga_dis.tmw_info
............................\............................\incremental_db\compiled_partitions\vga_dis.root_partition.map.kpt
............................\............................\..............\README
............................\............................\vga_dis.asm.rpt
............................\....................