文件名称:chrt35dg_SiGe
- 所属分类：
- 其他小程序
- 资源属性：
- 上传时间：
- 2014-08-09
- 文件大小：
- 2.29mb
- 下载次数：
- 0次
- 提 供 者：
- higgs*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
cadence virtuoso集成电路设计库，懂的人一定知道-cadence virtuoso
(系统自动生成,下载前可以参看下载内容)
下载文件列表
chrt35dg_SiGe
.............\.cdsenv
.............\2XPL_CON_V1
.............\...........\layout
.............\...........\......\layout.cdb
.............\...........\......\master.tag
.............\...........\......\pc.db
.............\BJT.Cat
.............\Capacitor.Cat
.............\cdsinfo.tag
.............\chrt35dg_SiGe.cdf
.............\chrt35dg_SiGe.cxt
.............\chrt35dg_SiGe.tf
.............\chrt35dg_SiGe.TopCat
.............\chrt35dg_SiGe64bit.cxt
.............\CON_04
.............\......\layout
.............\......\......\layout.cdb
.............\......\......\master.tag
.............\......\......\pc.db
.............\CON_V1
.............\......\layout
.............\......\......\layout.cdb
.............\......\......\master.tag
.............\......\......\pc.db
.............\co_040
.............\......\layout
.............\......\......\layout.cdb
.............\......\......\master.tag
.............\......\......\pc.db
.............\......\prop.xx
.............\co_0z40
.............\.......\layout
.............\.......\......\layout.cdb
.............\.......\......\master.tag
.............\.......\......\pc.db
.............\Diodes.Cat
.............\display.drf
.............\divaDRC.rul
.............\divaDRC_sige.rul
.............\divaEXT.rul
.............\divaLVS.rul
.............\fixed_layouts.Cat
.............\libInit.il
.............\libInitCustomExit.il
.............\lpnp
.............\....\ams
.............\....\...\master.tag
.............\....\...\pc.db
.............\....\...\symbol.cdb
.............\....\auCdl
.............\....\.....\master.tag
.............\....\.....\pc.db
.............\....\.....\symbol.cdb
.............\....\auLvs
.............\....\.....\master.tag
.............\....\.....\pc.db
.............\....\.....\symbol.cdb
.............\....\hspiceS
.............\....\.......\master.tag
.............\....\.......\pc.db
.............\....\.......\symbol.cdb
.............\....\ivpcell
.............\....\.......\layout.cdb
.............\....\.......\master.tag
.............\....\.......\pc.db
.............\....\prop.xx
.............\....\spectre
.............\....\.......\master.tag
.............\....\.......\pc.db
.............\....\.......\symbol.cdb
.............\....\symbol
.............\....\......\master.tag
.............\....\......\pc.db
.............\....\......\symbol.cdb
.............\....\UltraSim
.............\....\........\master.tag
.............\....\........\pc.db
.............\....\........\symbol.cdb
.............\LPNP_TN_10x10_L035
.............\..................\layout
.............\..................\......\layout.cdb
.............\..................\......\master.tag
.............\..................\......\pc.db
.............\LPNP_TN_1x1_L035
.............\................\layout
.............\................\......\layout.cdb
.............\................\......\master.tag
.............\................\......\pc.db
.............\LPNP_TN_2x2_L035
.............\................\layout
.............\................\......\layout.cdb
.............\................\......\master.tag
.............\................\......\pc.db
.............\LPNP_TN_5x5_L035
.............\................\layout
.............\................\......\layout.cdb
.............\................\......\master.tag
.............\................\......\pc.db
.............\LPNP_W1L12_F1_035