文件名称:shuzizhong
介绍说明－－下载内容均来自于网络，请自行研究使用
基于VeRILOG语言的多功能数字钟，已在FPGA板子上实现-Multi-function digital clock based VeRILOG language has been implemented on the FPGA board
(系统自动生成,下载前可以参看下载内容)
下载文件列表
shuzizhong\addr_ram.bsf
..........\addr_ram.vhd
..........\addr_ram.vhd.bak
..........\addr_ram1.bsf
..........\addr_ram1.vhd
..........\addr_ram1.vhd.bak
..........\addr_ram2.bsf
..........\addr_ram2.vhd
..........\addr_ram2.vhd.bak
..........\addr_ram3.bsf
..........\addr_ram3.vhd
..........\addr_ram3.vhd.bak
..........\ADDR_SEC.vwf
..........\altpll0.bsf
..........\altpll0.cmp
..........\altpll0.ppf
..........\altpll0.vhd
..........\altpll0_waveforms.html
..........\Block1.flow.rpt
..........\Block1.map.rpt
..........\Block1.map.summary
..........\Block1.qpf
..........\Block1.qsf
..........\block_name.vhd
..........\clock.asm.rpt
..........\clock.bdf
..........\clock.cdf
..........\clock.done
..........\clock.fit.rpt
..........\clock.fit.smsg
..........\clock.fit.summary
..........\clock.hex
..........\clock.jdi
..........\clock.map.summary
..........\clock.pin
..........\clock.pof
..........\clock.qpf
..........\clock.qsf
..........\clock.sim.rpt
..........\clock.sof
..........\clock.tan.rpt
..........\clock.tan.summary
..........\clock.tcl
..........\clock.tcl.bak
..........\conv.bsf
..........\conv.vhd
..........\conv.vhd.bak
..........\drive_led.bsf
..........\drive_led.vhd
..........\drive_led.vhd.bak
..........\fpq_1s.bsf
..........\fpq_1s.vhd
..........\fpq_1s.vhd.bak
..........\fpq_1s.vwf
..........\key1.bsf
..........\key1.vhd
..........\key1.vhd.bak
..........\key_buf.bsf
..........\key_buf.vhd
..........\key_buf.vhd.bak
..........\key_colv1.bsf
..........\key_colv1.vhd
..........\key_colv1.vhd.bak
..........\key_colv1.vwf
..........\lpm_rom0.bsf
..........\lpm_rom0.cmp
..........\lpm_rom0.vhd
..........\lpm_rom0_wave0.jpg
..........\lpm_rom0_waveforms.html
..........\my_or.bsf
..........\my_or.vhd
..........\my_or.vhd.bak
..........\secnd.bsf
..........\secnd.vhd
..........\secnd.vhd.bak
..........\secnd_out.bsf
..........\secnd_out.vhd
..........\secnd_out.vhd.bak
..........\sec_g.bsf
..........\sec_g.vhd
..........\sec_g.vhd.bak
..........\sec_s.bsf
..........\sec_s.vhd
..........\sec_s.vhd.bak
..........\shi_g.bsf
..........\shi_g.vhd
..........\shi_g.vhd.bak
..........\shi_s.bsf
..........\shi_s.vwf
..........\sopc_builder_log.txt
..........\stp1.stp
..........\db\add_sub_1rh.tdf
..........\..\add_sub_4rh.tdf
..........\..\add_sub_5rh.tdf
..........\..\add_sub_7rh.tdf
..........\..\add_sub_8rh.tdf
..........\..\add_sub_nsh.tdf
..........\..\altsyncram_et21.tdf
..........\..\altsyncram_qpo3.tdf
..........\..\altsyncram_spo3.tdf