文件名称:basicgates
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Verilog Code for Basic Gates implementation with testbench-Verilog Code for Basic Gates implementation with testbench..
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下载文件列表
basicgates
..........\2014-07-17-154752_1024x768_scrot.png
..........\behaviouralmodel
..........\................\not_and_or.v
..........\................\not_and_or.vcd
..........\................\not_and_or_tb.v
..........\................\not_and_or_tb.v~
..........\................\verilog.log
..........\dataflowmodel
..........\.............\basicgate
..........\.............\.........\basicgates.v
..........\.............\.........\basicgates.vcd
..........\.............\.........\basicgates.v~
..........\.............\.........\basicgates_tb.v
..........\.............\.........\basicgates_tb.v~
..........\.............\.........\verilog.log
..........\.............\basicgates.v~
..........\.............\basicgates_tb.v~
..........\.............\nandmodule
..........\.............\..........\nandgate.v
..........\.............\..........\nandgate.v~
..........\.............\..........\nandgate_tb.v
..........\.............\..........\nandgate_tb.v~
..........\.............\..........\nandmodule.vcd
..........\.............\..........\verilog.log