文件名称:traffic
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基于Verilog的交通灯，包含分频器模块、计数模块以及控制模块。状态机编写-Verilog-based traffic lights, including the divider block, counting module and a control module. Write state machine
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下载文件列表
traffic
.......\clk_div.v
.......\clk_div.v.bak
.......\clk_div_tb.v
.......\clk_div_tb.v.bak
.......\control.v
.......\control.v.bak
.......\control_tb.v
.......\control_tb.v.bak
.......\count.v
.......\count.v.bak
.......\count_tb.v
.......\count_tb.v.bak
.......\div_2.v.bak
.......\div_2_tb.v.bak
.......\traffic.cr.mti
.......\traffic.mpf
.......\traffic_top.v
.......\traffic_top.v.bak
.......\traffic_top_tb.v
.......\traffic_top_tb.v.bak
.......\vish_stacktrace.vstf
.......\vsim.wlf
.......\work
.......\....\@_opt
.......\....\.....\_deps
.......\....\.....\vopt5x759j
.......\....\.....\vopt65cjn2
.......\....\.....\vopt7dg14i
.......\....\.....\vopt8mkfh1
.......\....\.....\vopt9xrxyg
.......\....\.....\vopta5xbc0
.......\....\.....\voptf25hmj
.......\....\.....\voptga9z23
.......\....\.....\vopthiddgi
.......\....\.....\voptithvx1
.......\....\.....\voptj2n9bh
.......\....\.....\voptkatqr0
.......\....\.....\voptmiy56g
.......\....\.....\vopttf6bf3
.......\....\.....\voptvqaswi
.......\....\.....\voptwze7a2
.......\....\.....\voptx7jmqh
.......\....\.....\voptyfq351
.......\....\.....\voptzqvhig
.......\....\_info
.......\....\_temp
.......\....\.....\vlog28ztyc
.......\....\.....\vlog32g0f0
.......\....\.....\vlog4205gy
.......\....\.....\vlog49hgh4
.......\....\.....\vlog5q8hf9
.......\....\.....\vlog5vgtj6
.......\....\.....\vlogamg2gs
.......\....\.....\vlogbmd12j
.......\....\.....\vloge5f5fr
.......\....\.....\vlogehm6h3
.......\....\.....\vlogeswyvx
.......\....\.....\vloghigknm
.......\....\.....\vloghxw88n
.......\....\.....\vlogk6ve1a
.......\....\.....\vlogkrhm0y
.......\....\.....\vlogktykgz
.......\....\.....\vlogm6taev
.......\....\.....\vlogrcvadt
.......\....\.....\vlogrf0c3i
.......\....\.....\vlogrnfh1b
.......\....\.....\vlogsziein
.......\....\.....\vlogt62nxr
.......\....\.....\vlogvk5wms
.......\....\.....\vlogw4nzme
.......\....\.....\vlogx7gnfd
.......\....\.....\vlogyv01ws
.......\....\.....\vlogzqcexx
.......\....\_vmake
.......\....\clk_div
.......\....\.......\_primary.dat
.......\....\.......\_primary.dbs
.......\....\.......\_primary.vhd
.......\....\.......\verilog.asm
.......\....\.......\verilog.rw
.......\....\clk_div_tb
.......\....\..........\_primary.dat
.......\....\..........\_primary.dbs
.......\....\..........\_primary.vhd
.......\....\control
.......\....\.......\_primary.dat
.......\....\.......\_primary.dbs
.......\....\.......\_primary.vhd
.......\....\control_tb
.......\....\..........\_primary.dat
.......\....\..........\_primary.dbs
.......\....\..........\_primary.vhd
.......\....\count_60
.......\....\........\_primary.dat
.......\....\........\_primary.dbs
.......\....\........\_primary.vhd
.......\....\count_60_tb
.......\....\...........\_primary.dat
.......\....\...........\_primary.dbs