文件名称:PCIIP-core
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基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v”
Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and
write address generation and full, almost full, empty and almost empty status generation.
It also generates read and write allow signals, which are used for enabling/disabling
memory used for FIFO. Control logic can be used for independent read and write clocks.
Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and
write address generation and full, almost full, empty and almost empty status generation.
It also generates read and write allow signals, which are used for enabling/disabling
memory used for FIFO. Control logic can be used for independent read and write clocks.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
PCI的IP core\pci\bus_commands.v
............\...\bus_commands.vPreview
............\...\conf_space\conf_space.v
............\...\..........\conf_space.vPreview
............\...\..........\CVS\Entries
............\...\..........\...\Repository
............\...\..........\...\Root
............\...\constants.v
............\...\constants.v.bak
............\...\constants.vPreview
............\...\CVS\Entries
............\...\...\Entries.Log
............\...\...\Repository
............\...\...\Root
............\...\Decoder\CVS\Entries
............\...\.......\...\Repository
............\...\.......\...\Root
............\...\.......\decoder.v.TXT
............\...\.......\defines.v
............\...\.......\defines.vPreview
............\...\.......\readme.txt
............\...\.......\tb_decoder.v
............\...\.......\tb_decoder.vPreview
............\...\.......\tb_defines.v
............\...\.......\tb_defines.vPreview
............\...\delayed_sync\CVS\Entries
............\...\............\...\Repository
............\...\............\...\Root
............\...\............\delayed_sync.v
............\...\............\delayed_sync.vPreview
............\...\............\READ_ME.txt
............\...\.ocs\CVS\Entries
............\...\....\...\Repository
............\...\....\...\Root
............\...\....\pci_specification.pdf
............\...\.river\CVS\Entries
............\...\......\...\Repository
............\...\......\...\Root
............\...\......\README.txt
............\...\......\sdram_test
............\...\......\sdram_test.c
............\...\......\spartan_drv-2.2.o
............\...\......\spartan_drv-2.4.o
............\...\......\spartan_drv.c
............\...\......\spartan_kint.h
............\...\FIFOs\CVS\Entries
............\...\.....\...\Repository
............\...\.....\...\Root
............\...\.....\dp_async_ram.v
............\...\.....\dp_async_ram.vPreview
............\...\.....\dp_sram.v
............\...\.....\dp_sram.vPreview
............\...\.....\fifo_control.v
............\...\.....\fifo_control.vPreview
............\...\.....\pciw_pcir_fifos.v
............\...\.....\pciw_pcir_fifos.vPreview
............\...\.....\pci_tb.v
............\...\.....\pci_tb.vPreview
............\...\.....\read_me.pdf
............\...\.....\wbw_wbr_fifos.v
............\...\.....\wbw_wbr_fifos.vPreview
............\...\.....\wb_tb.v
............\...\.....\wb_tb.vPreview
............\...\conf_space\CVS
............\...\Decoder\CVS
............\...\delayed_sync\CVS
............\...\.ocs\CVS
............\...\.river\CVS
............\...\FIFOs\CVS
............\...\conf_space
............\...\CVS
............\...\Decoder
............\...\delayed_sync
............\...\docs
............\...\driver
............\...\FIFOs
............\pci
PCI的IP core