文件名称:Simple_Logic_Continue
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介绍说明－－下载内容均来自于网络，请自行研究使用
quartusII 9编写的74161模块，简单的例子，可以直接运行-The module 74161 with the language of verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Simple_Logic_Continue
.....................\74161_10.bdf
.....................\74161_10.vwf
.....................\74161_60.bdf
.....................\74161_60.vwf
.....................\D16.bdf
.....................\D16.vwf
.....................\HDL_60.bdf
.....................\Simple_Logic_Continue.asm.rpt
.....................\Simple_Logic_Continue.done
.....................\Simple_Logic_Continue.dpf
.....................\Simple_Logic_Continue.fit.rpt
.....................\Simple_Logic_Continue.fit.smsg
.....................\Simple_Logic_Continue.fit.summary
.....................\Simple_Logic_Continue.flow.rpt
.....................\Simple_Logic_Continue.map.rpt
.....................\Simple_Logic_Continue.map.summary
.....................\Simple_Logic_Continue.pin
.....................\Simple_Logic_Continue.pof
.....................\Simple_Logic_Continue.qpf
.....................\Simple_Logic_Continue.qsf
.....................\Simple_Logic_Continue.qws
.....................\Simple_Logic_Continue.sim.rpt
.....................\Simple_Logic_Continue.sof
.....................\Simple_Logic_Continue.sta.rpt
.....................\Simple_Logic_Continue.sta.summary
.....................\Simple_Logic_Continue.tan.rpt
.....................\Simple_Logic_Continue.tan.summary
.....................\Simple_Logic_Continue_assignment_defaults.qdf
.....................\Verilog_60.vwf
.....................\cntm60.bsf
.....................\cntm60.v
.....................\cntm60.v.bak
.....................\cntm60.vhd
.....................\cntm60.vhd.bak
.....................\db
.....................\..\Simple_Logic_Continue.asm.qmsg
.....................\..\Simple_Logic_Continue.asm.rdb
.....................\..\Simple_Logic_Continue.asm_labs.ddb
.....................\..\Simple_Logic_Continue.cbx.xml
.....................\..\Simple_Logic_Continue.cmp.bpm
.....................\..\Simple_Logic_Continue.cmp.cbp
.....................\..\Simple_Logic_Continue.cmp.cdb
.....................\..\Simple_Logic_Continue.cmp.ecobp
.....................\..\Simple_Logic_Continue.cmp.hdb
.....................\..\Simple_Logic_Continue.cmp.kpt
.....................\..\Simple_Logic_Continue.cmp.logdb
.....................\..\Simple_Logic_Continue.cmp.rdb
.....................\..\Simple_Logic_Continue.cmp_merge.kpt
.....................\..\Simple_Logic_Continue.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.....................\..\Simple_Logic_Continue.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.....................\..\Simple_Logic_Continue.db_info
.....................\..\Simple_Logic_Continue.eco.cdb
.....................\..\Simple_Logic_Continue.fit.qmsg
.....................\..\Simple_Logic_Continue.hier_info
.....................\..\Simple_Logic_Continue.hif
.....................\..\Simple_Logic_Continue.lpc.html
.....................\..\Simple_Logic_Continue.lpc.rdb
.....................\..\Simple_Logic_Continue.lpc.txt
.....................\..\Simple_Logic_Continue.map.bpm
.....................\..\Simple_Logic_Continue.map.cdb
.....................\..\Simple_Logic_Continue.map.ecobp
.....................\..\Simple_Logic_Continue.map.hdb
.....................\..\Simple_Logic_Continue.map.kpt
.....................\..\Simple_Logic_Continue.map.logdb
.....................\..\Simple_Logic_Continue.map.qmsg
.....................\..\Simple_Logic_Continue.map_bb.cdb
.....................\..\Simple_Logic_Continue.map_bb.hdb
.....................\..\Simple_Logic_Continue.map_bb.logdb
.....................\..\Simple_Logic_Continue.pre_map.cdb
.....................\..\Simple_Logic_Continue.pre_map.hdb
.....................\..\Simple_Logic_Continue.rtlv.hdb
.....................\..\Simple_Logic_Continue.rtlv_sg.cdb
.....................\..\Simple_Logic_Continue.rtlv_sg_swap.cdb
.....................\..\Simple_Logic_Continue.sgdiff.cdb
.....................\..\Simple_Logic_Continue.sgdiff.hdb
.....................\..\Simple_Logic_Continue.sim_ori.vwf
.....................\..\Simple_Logic_Continue.sld_design_entry.sci
.....................\..\Simple_Logic_Continue.sl