文件名称:pipeline10
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用verilog实现嵌入式系统的处理器的五级流水线。-realizing the five stages of cpu in the embedded system with the verilog language
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下载文件列表
pipeline10\EX.v
..........\EX_Alu.v
..........\EX_Branch.v
..........\EX_Forward.v
..........\EX_MEM.v
..........\EX_Membranch.v
..........\EX_Memread.v
..........\EX_Memwrite.v
..........\EX_Mux_rd.v
..........\EX_Mux_rt.v
..........\EX_Regwrite.v
..........\EX_Shift.v
..........\GLOBAL.v
..........\ID.v
..........\ID_Branch.v
..........\ID_Control.v
..........\ID_Data.v
..........\ID_EX.v
..........\ID_Hazard.v
..........\ID_ReadWrite.v
..........\IF.v
..........\IF_PC.v
..........\IF_REG.v
..........\MEM.v
..........\MEM_Branch.v
..........\MEM_EX_Error.v
..........\MEM_ReadWrite.v
..........\MEM_WB.v
..........\testbench.v
..........\TOP.v
..........\WB.v
pipeline10