文件名称:dds
介绍说明－－下载内容均来自于网络，请自行研究使用
在altera的FPGA上实现直接数字频率合成，即用verilog实现DDS，输出正弦波形，在modelsim软件中仿真通过，已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim software, already contains all the code and engineering as well as binary stream file.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
dds
...\pro
...\sim
...\...\DDS操作说明.doc
...\...\cos_data.dat
...\...\cos_data.txt
...\...\cos_data1.dat
...\...\cos_gen.m
...\...\dds_cos_rom.v
...\...\dds_cos_sin_block.v
...\...\dds_cos_sin_block.v.bak
...\...\dds_phas_acc.v
...\...\dds_sin_rom.v
...\...\fft_analyz_cos.m
...\...\fft_analyz_sin.m
...\...\sin_data.dat
...\...\sin_data.txt
...\...\sin_data1.dat
...\...\sin_gen.m
...\...\tb_dds_cos_sin_block .v
...\...\vsim.wlf
...\...\work
...\...\....\_info
...\...\....\_temp
...\...\....\.....\vlogfj81bw
...\...\....\.....\vlogfw818w
...\...\....\.....\vlogybqkfk
...\...\....\.....\vlogyrrk0k
...\...\....\_vmake
...\...\....\dds_cos_rom
...\...\....\...........\_primary.dat
...\...\....\...........\_primary.dbs
...\...\....\...........\_primary.vhd
...\...\....\...........\verilog.asm
...\...\....\...........\verilog.rw
...\...\....\dds_cos_sin_block
...\...\....\.................\_primary.dat
...\...\....\.................\_primary.dbs
...\...\....\.................\_primary.vhd
...\...\....\.................\verilog.asm
...\...\....\.................\verilog.rw
...\...\....\dds_phas_acc
...\...\....\............\_primary.dat
...\...\....\............\_primary.dbs
...\...\....\............\_primary.vhd
...\...\....\............\verilog.asm
...\...\....\............\verilog.rw
...\...\....\dds_sin_rom
...\...\....\...........\_primary.dat
...\...\....\...........\_primary.dbs
...\...\....\...........\_primary.vhd
...\...\....\...........\verilog.asm
...\...\....\...........\verilog.rw
...\...\....\tb_dds_cos_sin_block
...\...\....\....................\_primary.dat
...\...\....\....................\_primary.dbs
...\...\....\....................\_primary.vhd
...\...\....\....................\verilog.asm
...\...\....\....................\verilog.rw
...\src
...\...\dds_cos_rom.v
...\...\dds_cos_sin_block.v
...\...\dds_phas_acc.v
...\...\dds_sin_rom.v
...\...\pin.tcl
...\...\tb_dds_cos_sin_block .v