文件名称:mimajianceqi
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掌握时序电路的设计方法
掌握密码检测电路的设计完成密码检测电路的Verilog程序-module mimajianceqi(clock,reset,data1,data2,data3,data4,data5,data6,data7,data8,data_out)
input clock,reset,data1,data2,data3,data4,data5,data6,data7,data8
output data_out
reg data_out
reg[15:0] state
parameter
start_s=16 h0000,
first_s=16 h0001,
second_s=16 h0010,
third_s=16 h0011,
fourth_s=16 h0100,
fifth_s=16 h0101,
sixth_s=16 h0110,
seventh_s=16 h0111,
last_s=16 h1000
always@(posedge clock)
if(!reset)
begin
state<=start_s
data_out<=0
end
else
case(state)
start_s:
begin
data_out<=0
if(data6==1)
state<=first_s
else
state<=start_s
end
first_s:
begin
data_out<=0
if(data4==1)
state<=second_s
else
state<=start_s
end
second_s:
begin
data_out<=0
if(data8==1)
state<=third_s
else
state<=start_s
end
third_s:
begin
data_out<=0
if(data6==1)
state<=fourth_s
掌握密码检测电路的设计完成密码检测电路的Verilog程序-module mimajianceqi(clock,reset,data1,data2,data3,data4,data5,data6,data7,data8,data_out)
input clock,reset,data1,data2,data3,data4,data5,data6,data7,data8
output data_out
reg data_out
reg[15:0] state
parameter
start_s=16 h0000,
first_s=16 h0001,
second_s=16 h0010,
third_s=16 h0011,
fourth_s=16 h0100,
fifth_s=16 h0101,
sixth_s=16 h0110,
seventh_s=16 h0111,
last_s=16 h1000
always@(posedge clock)
if(!reset)
begin
state<=start_s
data_out<=0
end
else
case(state)
start_s:
begin
data_out<=0
if(data6==1)
state<=first_s
else
state<=start_s
end
first_s:
begin
data_out<=0
if(data4==1)
state<=second_s
else
state<=start_s
end
second_s:
begin
data_out<=0
if(data8==1)
state<=third_s
else
state<=start_s
end
third_s:
begin
data_out<=0
if(data6==1)
state<=fourth_s
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下载文件列表
mimajianceqi
............\db
............\..\mimajianceqi.asm.qmsg
............\..\mimajianceqi.cbx.xml
............\..\mimajianceqi.cmp.cdb
............\..\mimajianceqi.cmp.hdb
............\..\mimajianceqi.cmp.kpt
............\..\mimajianceqi.cmp.logdb
............\..\mimajianceqi.cmp.rdb
............\..\mimajianceqi.cmp.tdb
............\..\mimajianceqi.cmp0.ddb
............\..\mimajianceqi.db_info
............\..\mimajianceqi.dbp
............\..\mimajianceqi.eco.cdb
............\..\mimajianceqi.fit.qmsg
............\..\mimajianceqi.hier_info
............\..\mimajianceqi.hif
............\..\mimajianceqi.map.cdb
............\..\mimajianceqi.map.hdb
............\..\mimajianceqi.map.logdb
............\..\mimajianceqi.map.qmsg
............\..\mimajianceqi.pre_map.cdb
............\..\mimajianceqi.pre_map.hdb
............\..\mimajianceqi.psp
............\..\mimajianceqi.rpp.qmsg
............\..\mimajianceqi.rtlv.hdb
............\..\mimajianceqi.rtlv_sg.cdb
............\..\mimajianceqi.rtlv_sg_swap.cdb
............\..\mimajianceqi.sgate.rvd
............\..\mimajianceqi.sgate_sm.rvd
............\..\mimajianceqi.sgdiff.cdb
............\..\mimajianceqi.sgdiff.hdb
............\..\mimajianceqi.signalprobe.cdb
............\..\mimajianceqi.sld_design_entry.sci
............\..\mimajianceqi.sld_design_entry_dsc.sci
............\..\mimajianceqi.smp_dump.txt
............\..\mimajianceqi.syn_hier_info
............\..\mimajianceqi.tan.qmsg
............\mimajianceqi.asm.rpt
............\mimajianceqi.cdf
............\mimajianceqi.done
............\mimajianceqi.dpf
............\mimajianceqi.fit.rpt
............\mimajianceqi.fit.smsg
............\mimajianceqi.fit.summary
............\mimajianceqi.flow.rpt
............\mimajianceqi.map.rpt
............\mimajianceqi.map.summary
............\mimajianceqi.pin
............\mimajianceqi.pof
............\mimajianceqi.qpf
............\mimajianceqi.qsf
............\mimajianceqi.qws
............\mimajianceqi.sof
............\mimajianceqi.tan.rpt
............\mimajianceqi.tan.summary
............\mimajianceqi.v