文件名称:add

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2014-05-09
  • 文件大小:
  • 1.63mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 李*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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北京邮电大学VHDL课程作业,基于xilince ISE试验箱开发的,可以做简单的半加器加法-Beijing University of Posts and VHDL course work, based xilince ISE chamber developed, can do simple addition of half-adder
(系统自动生成,下载前可以参看下载内容)

下载文件列表





add

...\add.gise

...\add.ise

...\add.ntrc_log

...\add.vhd

...\add.xise

...\add_xdb

...\.......\cst.xbcd

...\.......\tmp

...\.......\...\ise

...\.......\...\ise.lock

...\.......\...\...\version

...\.......\...\...\__OBJSTORE__

...\.......\...\...\............\HierarchicalDesign

...\.......\...\...\............\..................\HDProject

...\.......\...\...\............\..................\.........\HDProject

...\.......\...\...\............\..................\.........\HDProject_StrTbl

...\.......\...\...\............\..................\__stored_object_table__

...\.......\...\...\............\PnAutoRun

...\.......\...\...\............\.........\Scripts

...\.......\...\...\............\.........\.......\RunOnce_tcl

...\.......\...\...\............\.........\.......\RunOnce_tcl_StrTbl

...\.......\...\...\............\ProjectNavigator

...\.......\...\...\............\ProjectNavigatorGui

...\.......\...\...\............\...................\CSourceProcessView

...\.......\...\...\............\...................\CSourceProcessView_StrTbl

...\.......\...\...\............\...................\CViewSelector

...\.......\...\...\............\...................\CViewSelector_StrTbl

...\.......\...\...\............\...................\File-SynthesisOnly

...\.......\...\...\............\...................\File-SynthesisOnly_StrTbl

...\.......\...\...\............\...................\Library-SynthesisOnly

...\.......\...\...\............\...................\Library-SynthesisOnly_StrTbl

...\.......\...\...\............\...................\Process-BehavioralSim-

...\.......\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE

...\.......\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl

...\.......\...\...\............\...................\Process-BehavioralSim-_StrTbl

...\.......\...\...\............\...................\Process-SynthesisOnly-

...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF

...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl

...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE

...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl

...\.......\...\...\............\...................\Process-SynthesisOnly-_StrTbl

...\.......\...\...\............\...................\Source-BehavioralSim-AutoCompile

...\.......\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl

...\.......\...\...\............\...................\Source-SynthesisOnly-AutoCompile

...\.......\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl

...\.......\...\...\............\................\dpm_project_main

...\.......\...\...\............\................\................\dpm_project_main

...\.......\...\...\............\................\................\dpm_project_main_StrTbl

...\.......\...\...\............\xreport

...\.......\...\...\............\.......\Gc_RvReportViewer-Current-Module

...\.......\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl

...\.......\...\...\............\.......\Gc_RvReportViewer-Module-Data-main

...\.......\...\...\............\.......\Gc_RvReportViewer-Module-Data-main_StrTbl

...\.......\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default

...\.......\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl

...\.......\...\...\__REGISTRY__

...\.......\...\...\............\Autonym

...\.......\...\...\............\.......\regkeys

...\.......\...\...\............\bitgen

...\.......\...\...\............\......\regkeys

...\.......\...\...\............\bitinit

...\.......\...\...\............\.......\regkeys

...\.......\...\...\............\common

...\.......\...\...\............\......\regkeys

...\.......\...\...\............\cpldfit

...\.......\...\...\............\.......\regkeys

...\.......\...\...\............\dumpngdio

...\.......\...\...\............\.

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