文件名称:ChengFaQi_mux16

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2014-04-30
  • 文件大小:
  • 798kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 望*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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实现16位乘法器 并有modelsim仿真文件-The realization of the 16 bit multiplier and Modelsim simulation file!!!!!!!!!!!!!!!!!!!!!!!!
(系统自动生成,下载前可以参看下载内容)

下载文件列表





ChengFaQi_mux16\db\logic_util_heursitic.dat

...............\..\mux16.asm.qmsg

...............\..\mux16.asm_labs.ddb

...............\..\mux16.cbx.xml

...............\..\mux16.cmp.cdb

...............\..\mux16.cmp.hdb

...............\..\mux16.cmp.kpt

...............\..\mux16.cmp.logdb

...............\..\mux16.cmp.rdb

...............\..\mux16.cmp.tdb

...............\..\mux16.cmp0.ddb

...............\..\mux16.db_info

...............\..\mux16.eco.cdb

...............\..\mux16.eda.qmsg

...............\..\mux16.fit.qmsg

...............\..\mux16.hier_info

...............\..\mux16.hif

...............\..\mux16.lpc.html

...............\..\mux16.lpc.rdb

...............\..\mux16.lpc.txt

...............\..\mux16.map.cdb

...............\..\mux16.map.hdb

...............\..\mux16.map.logdb

...............\..\mux16.map.qmsg

...............\..\mux16.pre_map.cdb

...............\..\mux16.pre_map.hdb

...............\..\mux16.rtlv.hdb

...............\..\mux16.rtlv_sg.cdb

...............\..\mux16.rtlv_sg_swap.cdb

...............\..\mux16.sgdiff.cdb

...............\..\mux16.sgdiff.hdb

...............\..\mux16.sim.cvwf

...............\..\mux16.sld_design_entry.sci

...............\..\mux16.sld_design_entry_dsc.sci

...............\..\mux16.syn_hier_info

...............\..\mux16.tan.qmsg

...............\..\mux16.tis_db_list.ddb

...............\..\mux16.tmw_info

...............\..\mux16_global_asgn_op.abo

...............\..\prev_cmp_mux16.asm.qmsg

...............\..\prev_cmp_mux16.eda.qmsg

...............\..\prev_cmp_mux16.fit.qmsg

...............\..\prev_cmp_mux16.map.qmsg

...............\..\prev_cmp_mux16.qmsg

...............\..\prev_cmp_mux16.tan.qmsg

...............\..\wed.wsf

...............\incremental_db\compiled_partitions\mux16.root_partition.map.kpt

...............\..............\README

...............\mux16.asm.rpt

...............\mux16.done

...............\mux16.eda.rpt

...............\mux16.fit.rpt

...............\mux16.fit.smsg

...............\mux16.fit.summary

...............\mux16.flow.rpt

...............\mux16.map.rpt

...............\mux16.map.smsg

...............\mux16.map.summary

...............\mux16.pin

...............\mux16.pof

...............\mux16.qpf

...............\mux16.qsf

...............\mux16.qws

...............\mux16.sim.rpt

...............\mux16.tan.rpt

...............\mux16.tan.summary

...............\mux16.v

...............\mux16.v.bak

...............\mux16.vwf

...............\mux16_assignment_defaults.qdf

...............\mux16_nativelink_simulation.rpt

...............\simulation\modelsim\maxii_atoms.v

...............\..........\........\modelsim.ini

...............\..........\........\msim_transcript

...............\..........\........\mux16.sft

...............\..........\........\mux16.vo

...............\..........\........\mux16_modelsim.xrf

...............\..........\........\mux16_run_msim_rtl_verilog.do

...............\..........\........\mux16_run_msim_rtl_verilog.do.bak

...............\..........\........\mux16_v.sdo

...............\..........\........\rtl_work\mux16\verilog.psm

...............\..........\........\........\.....\_primary.dat

...............\..........\........\........\.....\_primary.dbs

...............\..........\........\........\.....\_primary.vhd

...............\..........\........\........\vtf_test\verilog.psm

...............\..........\........\........\........\_primary.dat

...............\..........\........\........\........\_primary.dbs

...............\..........\........\........\........\_primary.vhd

...............\..........\........\........\_info

...............\..........\........\........\_vmake

...............\..........\........\vsim.wlf

...............\..........\........\vtf_test.v

...............\..........\........\rtl_work\mux16

...............\..........\........\........\vtf_test

...............\..........\........\........\_temp

...............\..........\........\rtl_work

...............\incremental_db\compiled_partitions

...............\simulation\modelsim

...............\db

...............\incremental_db

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