文件名称:COMPLETE-UART_16
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the project is complete a UART implementation where 16 UART are connect with top module for aerial applications-the project is complete a UART implementation where 16 UART are connect with top module for aerial applications
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下载文件列表
COMPLETE UART_16\RTL\CLK_DELAY.v
................\...\rx_uart.v
................\...\TOP_UART.v
................\...\TOP_UART_16.v
................\...\tx_uart.v
................\...\UART_FPGA.ucf
................\...\UART_FPGA.v
................\TEST BENCH\TEST_TOP_UART_16.v
................\..........\TEST_UART_FPGA.v
................\..........\TEST_UART_ONE.v
................\RTL
................\TEST BENCH
COMPLETE UART_16