文件名称:project3

  • 所属分类:
  • 其他小程序
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2014-04-13
  • 文件大小:
  • 154kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • mech****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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verilog 数码管循环显示两位数 可清零-verilog double-digit digital display can be cleared cycle
(系统自动生成,下载前可以参看下载内容)

下载文件列表





project3\clk_7segff_sub.v

........\clk_7segff_sub_summary.html

........\clk_7segff_top.bgn

........\clk_7segff_top.bit

........\clk_7segff_top.bld

........\clk_7segff_top.cmd_log

........\clk_7segff_top.drc

........\clk_7segff_top.lso

........\clk_7segff_top.ncd

........\clk_7segff_top.ngc

........\clk_7segff_top.ngd

........\clk_7segff_top.ngr

........\clk_7segff_top.pad

........\clk_7segff_top.par

........\clk_7segff_top.pcf

........\clk_7segff_top.prj

........\clk_7segff_top.ptwx

........\clk_7segff_top.stx

........\clk_7segff_top.syr

........\clk_7segff_top.twr

........\clk_7segff_top.twx

........\clk_7segff_top.ucf

........\clk_7segff_top.unroutes

........\clk_7segff_top.ut

........\clk_7segff_top.v

........\clk_7segff_top.xpi

........\clk_7segff_top.xst

........\clk_7segff_top_bitgen.xwbt

........\clk_7segff_top_envsettings.html

........\clk_7segff_top_guide.ncd

........\clk_7segff_top_map.map

........\clk_7segff_top_map.mrp

........\clk_7segff_top_map.ncd

........\clk_7segff_top_map.ngm

........\clk_7segff_top_map.xrpt

........\clk_7segff_top_ngdbuild.xrpt

........\clk_7segff_top_pad.csv

........\clk_7segff_top_pad.txt

........\clk_7segff_top_par.xrpt

........\clk_7segff_top_summary.html

........\clk_7segff_top_summary.xml

........\clk_7segff_top_usage.xml

........\clk_7segff_top_xst.xrpt

........\iseconfig\clk_7segff_sub.xreport

........\.........\clk_7segff_top.xreport

........\.........\project3.projectmgr

........\pa.fromHdl.tcl

........\planAhead_pid7900.debug

........\..........run_1\planAhead.jou

........\...............\planAhead.log

........\...............\planAhead_run.log

........\...............\.roject3.data\constrs_1\designprops.xml

........\...............\.............\.........\fileset.xml

........\...............\.............\.........\usercols.xml

........\...............\.............\sim_1\fileset.xml

........\...............\.............\.ources_1\fileset.xml

........\...............\.............\.........\ports.xml

........\...............\.............\wt\java_command_handlers.wdf

........\...............\.............\..\project.wpc

........\...............\.............\..\webtalk_pa.xml

........\...............\project3.ppr

........\project3.gise

........\project3.xise

........\usage_statistics_webtalk.html

........\webtalk.log

........\webtalk_pn.xml

........\xlnx_auto_0_xdb\cst.xbcd

........\.st\work\hdllib.ref

........\...\....\vlg24\clk__7segff__sub.bin

........\...\....\....D\clk__7segff__top.bin

........\_ngo\netlist.lst

........\.xmsgs\bitgen.xmsgs

........\......\map.xmsgs

........\......\ngdbuild.xmsgs

........\......\par.xmsgs

........\......\pn_parser.xmsgs

........\......\trce.xmsgs

........\......\xst.xmsgs

........\xst\dump.xst\clk_7segff_top.prj\ngx\notopt

........\...\........\..................\...\opt

........\...\........\..................\ngx

........\planAhead_run_1\project3.data\constrs_1

........\...............\.............\sim_1

........\...............\.............\sources_1

........\...............\.............\wt

........\xst\dump.xst\clk_7segff_top.prj

........\...\work\vlg24

........\...\....\vlg2D

........\planAhead_run_1\project3.data

........\xst\dump.xst

........\...\projnav.tmp

........\...\work

........\ipcore_dir

........\iseconfig

........\planAhead_run_1

........\xlnx_auto_0_xdb

........\xst

........\_ngo

........\_xmsgs

project3

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