5

.\Quartus

.\.......\VGA_CTL.asm.rpt

.\.......\VGA_CTL.done

.\.......\VGA_CTL.dpf

.\.......\VGA_CTL.fit.rpt

.\.......\VGA_CTL.fit.smsg

.\.......\VGA_CTL.fit.summary

.\.......\VGA_CTL.flow.rpt

.\.......\VGA_CTL.map.rpt

.\.......\VGA_CTL.map.summary

.\.......\VGA_CTL.pin

.\.......\VGA_CTL.pof

.\.......\VGA_CTL.qpf

.\.......\VGA_CTL.qsf

.\.......\VGA_CTL.qws

.\.......\VGA_CTL.sof

.\.......\VGA_CTL.tan.rpt

.\.......\VGA_CTL.tan.summary

.\.......\db

.\.......\..\VGA.db_info

.\.......\..\VGA.eco.cdb

.\.......\..\VGA.sld_design_entry.sci

.\.......\..\VGA_CTL.asm.qmsg

.\.......\..\VGA_CTL.asm_labs.ddb

.\.......\..\VGA_CTL.cbx.xml

.\.......\..\VGA_CTL.cmp.bpm

.\.......\..\VGA_CTL.cmp.cdb

.\.......\..\VGA_CTL.cmp.ecobp

.\.......\..\VGA_CTL.cmp.hdb

.\.......\..\VGA_CTL.cmp.kpt

.\.......\..\VGA_CTL.cmp.logdb

.\.......\..\VGA_CTL.cmp.rdb

.\.......\..\VGA_CTL.cmp.tdb

.\.......\..\VGA_CTL.cmp0.ddb

.\.......\..\VGA_CTL.cmp2.ddb

.\.......\..\VGA_CTL.cmp_merge.kpt

.\.......\..\VGA_CTL.db_info

.\.......\..\VGA_CTL.eco.cdb

.\.......\..\VGA_CTL.fit.qmsg

.\.......\..\VGA_CTL.hier_info

.\.......\..\VGA_CTL.hif

.\.......\..\VGA_CTL.lpc.html

.\.......\..\VGA_CTL.lpc.rdb

.\.......\..\VGA_CTL.lpc.txt

.\.......\..\VGA_CTL.map.bpm

.\.......\..\VGA_CTL.map.cdb

.\.......\..\VGA_CTL.map.ecobp

.\.......\..\VGA_CTL.map.hdb

.\.......\..\VGA_CTL.map.kpt

.\.......\..\VGA_CTL.map.logdb

.\.......\..\VGA_CTL.map.qmsg

.\.......\..\VGA_CTL.map_bb.cdb

.\.......\..\VGA_CTL.map_bb.hdb

.\.......\..\VGA_CTL.map_bb.logdb

.\.......\..\VGA_CTL.pre_map.cdb

.\.......\..\VGA_CTL.pre_map.hdb

.\.......\..\VGA_CTL.rtlv.hdb

.\.......\..\VGA_CTL.rtlv_sg.cdb

.\.......\..\VGA_CTL.rtlv_sg_swap.cdb

.\.......\..\VGA_CTL.sgdiff.cdb

.\.......\..\VGA_CTL.sgdiff.hdb

.\.......\..\VGA_CTL.sld_design_entry.sci

.\.......\..\VGA_CTL.sld_design_entry_dsc.sci

.\.......\..\VGA_CTL.syn_hier_info

.\.......\..\VGA_CTL.tan.qmsg

.\.......\..\VGA_CTL.tis_db_list.ddb

.\.......\..\VGA_CTL.tmw_info

.\.......\..\VGA_CTL_global_asgn_op.abo

.\.......\..\altsyncram_3881.tdf

.\.......\..\prev_cmp_VGA_CTL.asm.qmsg

.\.......\..\prev_cmp_VGA_CTL.fit.qmsg

.\.......\..\prev_cmp_VGA_CTL.map.qmsg

.\.......\..\prev_cmp_VGA_CTL.qmsg

.\.......\..\prev_cmp_VGA_CTL.tan.qmsg

.\.......\incremental_db

.\.......\..............\README

.\.......\..............\compiled_partitions

.\.......\..............\...................\VGA_CTL.root_partition.cmp.atm

.\.......\..............\...................\VGA_CTL.root_partition.cmp.dfp

.\.......\..............\...................\VGA_CTL.root_partition.cmp.hdbx

.\.......\..............\...................\VGA_CTL.root_partition.cmp.kpt

.\.......\..............\...................\VGA_CTL.root_partition.cmp.logdb

.\.......\..............\...................\VGA_CTL.root_partition.cmp.rcf

.\.......\..............\...................\VGA_CTL.root_partition.map.atm

.\.......\..............\...................\VGA_CTL.root_partition.map.dpi

.\.......\..............\...................\VGA_CTL.root_partition.map.hdbx

.\.......\..............\...................\VGA_CTL.root_partition.map.kpt

.\Testbench

.\.........\VGA_tb.v

.\.........\altera_mf.v

.\modelsim

.\........\VGA.cr.mti

.\........\VGA.mpf

.\........\transcript

.\........\vga.do

.\........\vsim.wlf

.\........\work

.\........\....\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s

.\........\....\..........................................\_primary.dat