文件名称:finaldesign_watch
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基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for the development, the use of the VHDL language, from 0.01 seconds to 59 minutes 59 seconds 59 design.
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下载文件列表
finaldesign数字跑表
...................\Block.asm.rpt
...................\Block.bdf
...................\Block.done
...................\Block.dpf
...................\Block.fit.rpt
...................\Block.fit.summary
...................\Block.flow.rpt
...................\Block.map.rpt
...................\Block.map.summary
...................\Block.pin
...................\Block.pof
...................\Block.qpf
...................\Block.qsf
...................\Block.qws
...................\Block.sim.rpt
...................\Block.sof
...................\Block.tan.rpt
...................\Block.tan.summary
...................\Block.vwf
...................\clk_div10.bsf
...................\clk_div10.vhd
...................\clk_div10.vhd.bak
...................\db
...................\..\add_sub_0ih.tdf
...................\..\add_sub_jlh.tdf
...................\..\add_sub_klh.tdf
...................\..\Block.asm.qmsg
...................\..\Block.cbx.xml
...................\..\Block.cmp.cdb
...................\..\Block.cmp.hdb
...................\..\Block.cmp.logdb
...................\..\Block.cmp.rdb
...................\..\Block.cmp.tdb
...................\..\Block.cmp0.ddb
...................\..\Block.db_info
...................\..\Block.eco.cdb
...................\..\Block.eds_overflow
...................\..\Block.fit.qmsg
...................\..\Block.fnsim.hdb
...................\..\Block.fnsim.qmsg
...................\..\Block.hier_info
...................\..\Block.hif
...................\..\Block.lpc.html
...................\..\Block.lpc.rdb
...................\..\Block.lpc.txt
...................\..\Block.map.cdb
...................\..\Block.map.hdb
...................\..\Block.map.logdb
...................\..\Block.map.qmsg
...................\..\Block.pre_map.cdb
...................\..\Block.pre_map.hdb
...................\..\Block.rtlv.hdb
...................\..\Block.rtlv_sg.cdb
...................\..\Block.rtlv_sg_swap.cdb
...................\..\Block.sgdiff.cdb
...................\..\Block.sgdiff.hdb
...................\..\Block.sim.cvwf
...................\..\Block.sim.hdb
...................\..\Block.sim.qmsg
...................\..\Block.sim.rdb
...................\..\Block.simfam
...................\..\Block.sld_design_entry.sci
...................\..\Block.sld_design_entry_dsc.sci
...................\..\Block.syn_hier_info
...................\..\Block.tan.qmsg
...................\..\Block.tis_db_list.ddb
...................\..\Block.tmw_info
...................\..\mux_hbc.tdf
...................\..\p2.asm.qmsg
...................\..\p2.cbx.xml
...................\..\p2.cmp.cdb
...................\..\p2.cmp.hdb
...................\..\p2.cmp.logdb
...................\..\p2.cmp.rdb
...................\..\p2.cmp.tdb
...................\..\p2.cmp0.ddb
...................\..\p2.db_info
...................\..\p2.eco.cdb
...................\..\p2.fit.qmsg
...................\..\p2.hier_info
...................\..\p2.hif
...................\..\p2.lpc.html
...................\..\p2.lpc.rdb
...................\..\p2.lpc.txt
...................\..\p2.map.cdb
...................\..\p2.map.hdb
...................\..\p2.map.logdb
...................\..\p2.map.qmsg
...................\..\p2.pre_map.cdb
...................\..\p2.pre_map.hdb
...................\..\p2.rtlv.hdb
...................\..\p2.rtlv_sg.cdb
...................\..\p2.rtlv_sg_swap.cdb
...................\..\p2.sgdiff.cdb
...................\..\p2.sgdiff.hdb
...................\..\p2.sld_design_entry.sci
...................\..\p2.sld_design_entry_dsc.sci
...................\..\p2.syn_hier_info
...................\..\p2.tan.qmsg