文件名称:test
介绍说明－－下载内容均来自于网络，请自行研究使用
可以在四个七段数码管上循环显示两个不同的学号-
You can cycle through two different student number on the four seven-segment LED
You can cycle through two different student number on the four seven-segment LED
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test\db\prev_cmp_Verilog1.asm.qmsg
....\..\prev_cmp_Verilog1.fit.qmsg
....\..\prev_cmp_Verilog1.map.qmsg
....\..\prev_cmp_Verilog1.qmsg
....\..\prev_cmp_Verilog1.sta.qmsg
....\..\prev_cmp_Verilog1.tan.qmsg
....\..\Verilog1.asm.qmsg
....\..\Verilog1.asm_labs.ddb
....\..\Verilog1.cbx.xml
....\..\Verilog1.cmp.bpm
....\..\Verilog1.cmp.cdb
....\..\Verilog1.cmp.ecobp
....\..\Verilog1.cmp.hdb
....\..\Verilog1.cmp.kpt
....\..\Verilog1.cmp.logdb
....\..\Verilog1.cmp.rdb
....\..\Verilog1.cmp_merge.kpt
....\..\Verilog1.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
....\..\Verilog1.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
....\..\Verilog1.db_info
....\..\Verilog1.eco.cdb
....\..\Verilog1.fit.qmsg
....\..\Verilog1.hier_info
....\..\Verilog1.hif
....\..\Verilog1.lpc.html
....\..\Verilog1.lpc.rdb
....\..\Verilog1.lpc.txt
....\..\Verilog1.map.bpm
....\..\Verilog1.map.cdb
....\..\Verilog1.map.ecobp
....\..\Verilog1.map.hdb
....\..\Verilog1.map.kpt
....\..\Verilog1.map.logdb
....\..\Verilog1.map.qmsg
....\..\Verilog1.map_bb.cdb
....\..\Verilog1.map_bb.hdb
....\..\Verilog1.map_bb.logdb
....\..\Verilog1.pre_map.cdb
....\..\Verilog1.pre_map.hdb
....\..\Verilog1.rtlv.hdb
....\..\Verilog1.rtlv_sg.cdb
....\..\Verilog1.rtlv_sg_swap.cdb
....\..\Verilog1.sgdiff.cdb
....\..\Verilog1.sgdiff.hdb
....\..\Verilog1.sld_design_entry.sci
....\..\Verilog1.sld_design_entry_dsc.sci
....\..\Verilog1.sta.qmsg
....\..\Verilog1.sta.rdb
....\..\Verilog1.sta_cmp.6_slow_1200mv_85c.tdb
....\..\Verilog1.syn_hier_info
....\..\Verilog1.tan.qmsg
....\..\Verilog1.tiscmp.fast_1200mv_0c.ddb
....\..\Verilog1.tiscmp.slow_1200mv_0c.ddb
....\..\Verilog1.tiscmp.slow_1200mv_85c.ddb
....\..\Verilog1.tis_db_list.ddb
....\..\Verilog1.tmw_info
....\..\Verilog1_global_asgn_op.abo
....\incremental_db\compiled_partitions\Verilog1.root_partition.cmp.atm
....\..............\...................\Verilog1.root_partition.cmp.dfp
....\..............\...................\Verilog1.root_partition.cmp.hdbx
....\..............\...................\Verilog1.root_partition.cmp.kpt
....\..............\...................\Verilog1.root_partition.cmp.logdb
....\..............\...................\Verilog1.root_partition.cmp.rcf
....\..............\...................\Verilog1.root_partition.map.atm
....\..............\...................\Verilog1.root_partition.map.dpi
....\..............\...................\Verilog1.root_partition.map.hdbx
....\..............\...................\Verilog1.root_partition.map.kpt
....\..............\README
....\Verilog1.asm.rpt
....\Verilog1.cdf
....\Verilog1.done
....\Verilog1.dpf
....\Verilog1.fit.rpt
....\Verilog1.fit.summary
....\Verilog1.flow.rpt
....\Verilog1.map.rpt
....\Verilog1.map.summary
....\Verilog1.pin
....\Verilog1.pof
....\Verilog1.qpf
....\Verilog1.qsf
....\Verilog1.qws
....\Verilog1.sof
....\Verilog1.sta.rpt
....\Verilog1.sta.summary
....\Verilog1.tan.rpt
....\Verilog1.tan.summary
....\Verilog1.v
....\Verilog1.v.bak
....\Verilog1_description.txt
....\incremental_db\compiled_partitions
....\db
....\incremental_db
test