文件名称:uart2bus_latest

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  • 其他小程序
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  • [PDF]
  • 上传时间:
  • 2013-12-30
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  • 1.16mb
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  • vinc*****
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uart2bus_latest\uart2bus_latest\uart2bus\trunk\doc\UART to Bus Core Specifications.pdf

...............\...............\........\.....\vhdl\bench\uart2BusTop_bin_tb.vhd

...............\...............\........\.....\....\.....\regFileModel.vhd

...............\...............\........\.....\....\.....\uart2BusTop_txt_tb.vhd

...............\...............\........\.....\....\syn\xilinx\uart2bus.xise

...............\...............\........\.....\....\rtl\uart2BusTop.vhd

...............\...............\........\.....\....\...\uartTop.vhd

...............\...............\........\.....\....\...\baudGen.vhd

...............\...............\........\.....\....\...\uartRx.vhd

...............\...............\........\.....\....\...\uartParser.vhd

...............\...............\........\.....\....\...\uartTx.vhd

...............\...............\........\.....\....\test.txt

...............\...............\........\.....\....\test.bin

...............\...............\........\.....\scilab\calc_baud_gen.sce

...............\...............\........\.....\verilog\bench\timescale.v

...............\...............\........\.....\.......\.....\tb_txt_uart2bus_top.v

...............\...............\........\.....\.......\.....\tb_bin_uart2bus_top.v

...............\...............\........\.....\.......\.....\uart_tasks.v

...............\...............\........\.....\.......\.....\tb_uart2bus_top.v

...............\...............\........\.....\.......\.....\reg_file_model.v

...............\...............\........\.....\.......\sim\icarus\run.bat

...............\...............\........\.....\.......\...\......\gtk.bat

...............\...............\........\.....\.......\...\......\block_txt.cfg

...............\...............\........\.....\.......\...\......\compile_txt.bat

...............\...............\........\.....\.......\...\......\test.txt

...............\...............\........\.....\.......\...\......\test.bin

...............\...............\........\.....\.......\...\......\compile_bin.bat

...............\...............\........\.....\.......\...\......\block_bin.cfg

...............\...............\........\.....\.......\.yn\altera\uart2bus_top.qsf

...............\...............\........\.....\.......\...\......\uart2bus.qpf

...............\...............\........\.....\.......\...\......\uart2bus.qws

...............\...............\........\.....\.......\...\xilinx\uart2bus.xise

...............\...............\........\.....\.......\rtl\uart_rx.v

...............\...............\........\.....\.......\...\uart2bus_top.v

...............\...............\........\.....\.......\...\uart_tx.v

...............\...............\........\.....\.......\...\baud_gen.v

...............\...............\........\.....\.......\...\uart_top.v

...............\...............\........\.....\.......\...\uart_parser.v

...............\...............\........\.....\QUARTUS2\starter_uart2bus.qpf

...............\...............\........\.....\........\starter_uart2bus.qsf

...............\...............\........\.....\........\starter_uart2bus.map.summary

...............\...............\........\.....\........\starter_uart2bus.dpf

...............\...............\........\.....\........\starter_uart2bus_description.txt

...............\...............\........\.....\........\starter_uart2bus.pin

...............\...............\........\.....\........\starter_uart2bus.fit.smsg

...............\...............\........\.....\........\starter_uart2bus.fit.summary

...............\...............\........\.....\........\starter_uart2bus.sof

...............\...............\........\.....\........\starter_uart2bus.pof

...............\...............\........\.....\........\starter_uart2bus.done

...............\...............\........\.....\........\........src\m_dynamic_seg7.v

...............\...............\........\.....\........\...........\fpga_starter_pin.tcl.bak

...............\...............\........\.....\........\...........\fpga_starter_pin.tcl

...............\...............\........\.....\........\...........\starter_uart2bus.v.bak

.......

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