c4gx_qsys_pcie_gen1x1

.....................\.qsys_edit

.....................\..........\filters.xml

.....................\..........\preferences.xml

.....................\altgx_reconfig.qip

.....................\altgx_reconfig.v

.....................\altgx_reconfig_bb.v

.....................\c4gx_qsys_pcie_gen1x1.qpf

.....................\ip

.....................\..\Read_Master

.....................\..\...........\MM_to_ST_Adapter.v

.....................\..\...........\Modular_SGDMA_Read_Master_Core_UG.pdf

.....................\..\...........\read_burst_control.v

.....................\..\...........\read_master.v

.....................\..\...........\read_master_hw.tcl

.....................\..\SGDMA_dispatcher

.....................\..\................\csr_block.v

.....................\..\................\descriptor_buffers.v

.....................\..\................\dispatcher.v

.....................\..\................\dispatcher_hw.tcl

.....................\..\................\dispatcher_sw.tcl

.....................\..\................\fifo_with_byteenables.v

.....................\..\................\HAL

.....................\..\................\...\inc

.....................\..\................\...\...\sgdma_dispatcher.h

.....................\..\................\...\src

.....................\..\................\...\...\component.mk

.....................\..\................\...\...\sgdma_dispatcher.c

.....................\..\................\inc

.....................\..\................\...\csr_regs.h

.....................\..\................\...\descriptor_regs.h

.....................\..\................\...\response_regs.h

.....................\..\................\Modular_SGDMA_Dispatcher_Core_UG.pdf

.....................\..\................\read_signal_breakout.v

.....................\..\................\response_block.v

.....................\..\................\write_signal_breakout.v

.....................\..\Write_Master

.....................\..\............\byte_enable_generator.v

.....................\..\............\Modular_SGDMA_Write_Master_Core_UG.pdf

.....................\..\............\ST_to_MM_Adapter.v

.....................\..\............\write_burst_control.v

.....................\..\............\write_master.v

.....................\..\............\write_master_hw.tcl

.....................\out_directory_tmp.txt.tmp

.....................\PLLJ_PLLSPE_INFO.txt

.....................\qii_seed_sweep.tcl

.....................\q_sys

.....................\.....\synthesis

.....................\.....\.........\q_sys.qip

.....................\.....\.........\q_sys.v

.....................\.....\.........\submodules

.....................\.....\.........\..........\altera_avalon_mm_bridge.v

.....................\.....\.........\..........\altera_avalon_sc_fifo.v

.....................\.....\.........\..........\altera_avalon_st_pipeline_base.v

.....................\.....\.........\..........\altera_avalon_st_pipeline_stage.sv

.....................\.....\.........\..........\altera_irq_clock_crosser.sv

.....................\.....\.........\..........\altera_merlin_arbitrator.sv

.....................\.....\.........\..........\altera_merlin_burst_adapter.sv

.....................\.....\.........\..........\altera_merlin_burst_uncompressor.sv

.....................\.....\.........\..........\altera_merlin_master_agent.sv

.....................\.....\.........\..........\altera_merlin_master_translator.sv

.....................\.....\.........\..........\altera_merlin_slave_agent.sv

.....................\.....\.........\..........\altera_merlin_slave_translator.sv

.....................\.....\.........\..........\altera_merlin_traffic_limiter.sv

.....................\.....\.........\..........\altera_merlin_width_adapter.sv

.....................\.....\.........\..........\altera_pcie_hard_ip_reset_controller.v

.....................\.....\.........\..........\altera_pci_express.sdc

.....................\.....\.........\..........\altera_reset_controller.sdc

.....................\.....\.........\..........\altera_reset_contro