文件名称:cordic
- 所属分类：
- VHDL编程
- 资源属性：
- [HTML]
- 上传时间：
- 2013-11-19
- 文件大小：
- 133kb
- 下载次数：
- 0次
- 提 供 者：
- thangap*******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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cordic processor design in vhdl
(系统自动生成,下载前可以参看下载内容)
下载文件列表
cordic\addsub.lso
......\addsub.prj
......\addsub.stx
......\addsub.xst
......\addsub_synthesis.vhd
......\atan32_Arch1.vhd
......\behavioral.vhd
......\clockgen.lso
......\clockgen.prj
......\clockgen.stx
......\clockgen.xst
......\clockgen_rtl.vhd
......\cordic.gise
......\cordic.lso
......\cordic.prj
......\cordic.stx
......\cordic.xise
......\cordic.xst
......\cordic_pkg.lso
......\cordic_pkg.prj
......\cordic_pkg.stx
......\cordic_pkg.xst
......\cordic_pkg_pkg.vhd
......\cordic_synthesis.vhd
......\cordic_tb.cmd_log
......\cordic_tb.lso
......\cordic_tb.prj
......\cordic_tb.stx
......\cordic_tb.syr
......\cordic_tb.xst
......\cordic_tb_envsettings.html
......\cordic_tb_struct.vhd
......\cordic_tb_summary.html
......\cordic_tb_xst.xrpt
......\cordic_tester.lso
......\cordic_tester.prj
......\cordic_tester.stx
......\cordic_tester.xst
......\cordic_tester_behavioral.vhd
......\fsm_synthesis.vhd
......\hdl\addsub_synthesis.vhd
......\...\atan32_Arch1.vhd
......\...\clockgen_rtl.vhd
......\...\cordic_pkg_pkg.vhd
......\...\cordic_synthesis.vhd
......\...\cordic_tb_struct.vhd
......\...\cordic_tester_behavioral.vhd
......\...\fsm_synthesis.vhd
......\...\shiftn_synthesis.vhd
......\iseconfig\cordic.projectmgr
......\.........\cordic_tb.xreport
......\shiftn_synthesis.vhd
......\.rc\.xrf\addsub_synthesis.xrf
......\...\....\atan32_Arch1.xrf
......\...\....\clockgen_rtl.xrf
......\...\....\cordic_pkg_pkg.xrf
......\...\....\cordic_pkg_pkg_body.xrf
......\...\....\cordic_synthesis.xrf
......\...\....\cordic_tb_struct.xrf
......\...\....\cordic_tester_behavioral.xrf
......\...\....\fsm_synthesis.xrf
......\...\....\shiftn_synthesis.xrf
......\...\addsub\default_view
......\...\......\symbol.sb
......\...\......\synthesis.vhd
......\...\......\..............info\structure.dh
......\...\.tan32\Arch1.vhd
......\...\......\..........info\structure.dh
......\...\......\default_view
......\...\......\symbol.sb
......\...\clockgen\default_view
......\...\........\rtl.vhd
......\...\........\........info\structure.dh
......\...\........\symbol.sb
......\...\.ordic\default_view
......\...\......\symbol.sb
......\...\......\synthesis.bd
......\...\......_pkg\cordic_pkg.info\structure.dh
......\...\..........\_package.vhd
......\...\..........\_package_body.vhd
......\...\.......tb\default_view
......\...\.........\struct.bd
......\...\.........\symbol.sb
......\...\........ester\behavioral.vhd
......\...\.............\...............info\structure.dh
......\...\.............\...................\testvec.txt
......\...\.............\default_view
......\...\.............\interface
......\...\fsm\default_view
......\...\...\symbol.sb
......\...\...\synthesis.sm
......\...\shiftn\default_view
......\...\......\symbol.sb
......\...\......\synthesis.vhd
......\...\......\..............info\structure.dh
......\testvec.txt
......\webtalk_pn.xml
......\.ork_mti\compile.scr
......\........\modelsim.ini
......\........\modelsim.tcl